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author | Clifford Wolf <clifford@clifford.at> | 2016-10-12 01:18:39 +0200 |
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committer | Clifford Wolf <clifford@clifford.at> | 2016-10-12 01:18:39 +0200 |
commit | 8ebba8a35f0a5dbf3a044ab84575edfc46c99d77 (patch) | |
tree | 180fce8de63b6908d00ccefb59a6f9a3a930b5a4 /kernel/rtlil.cc | |
parent | 4a981a3bd81836cd15059db56f01b60b11068742 (diff) | |
download | yosys-8ebba8a35f0a5dbf3a044ab84575edfc46c99d77.tar.gz yosys-8ebba8a35f0a5dbf3a044ab84575edfc46c99d77.tar.bz2 yosys-8ebba8a35f0a5dbf3a044ab84575edfc46c99d77.zip |
Added $ff and $_FF_ cell types
Diffstat (limited to 'kernel/rtlil.cc')
-rw-r--r-- | kernel/rtlil.cc | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 32efe4f0d..b0cda67b4 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -866,6 +866,13 @@ namespace { return; } + if (cell->type == "$ff") { + port("\\D", param("\\WIDTH")); + port("\\Q", param("\\WIDTH")); + check_expected(); + return; + } + if (cell->type == "$dff") { param_bool("\\CLK_POLARITY"); port("\\CLK", 1); @@ -1069,6 +1076,7 @@ namespace { if (cell->type == "$_SR_PN_") { check_gate("SRQ"); return; } if (cell->type == "$_SR_PP_") { check_gate("SRQ"); return; } + if (cell->type == "$_FF_") { check_gate("DQ"); return; } if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; } if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; } @@ -1830,6 +1838,15 @@ RTLIL::Cell* RTLIL::Module::addSr(RTLIL::IdString name, RTLIL::SigSpec sig_set, return cell; } +RTLIL::Cell* RTLIL::Module::addFf(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q) +{ + RTLIL::Cell *cell = addCell(name, "$ff"); + cell->parameters["\\WIDTH"] = sig_q.size(); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); + return cell; +} + RTLIL::Cell* RTLIL::Module::addDff(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) { RTLIL::Cell *cell = addCell(name, "$dff"); @@ -1912,6 +1929,14 @@ RTLIL::Cell* RTLIL::Module::addDlatchsr(RTLIL::IdString name, RTLIL::SigSpec sig return cell; } +RTLIL::Cell* RTLIL::Module::addFfGate(RTLIL::IdString name, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q) +{ + RTLIL::Cell *cell = addCell(name, "$_FF_"); + cell->setPort("\\D", sig_d); + cell->setPort("\\Q", sig_q); + return cell; +} + RTLIL::Cell* RTLIL::Module::addDffGate(RTLIL::IdString name, RTLIL::SigSpec sig_clk, RTLIL::SigSpec sig_d, RTLIL::SigSpec sig_q, bool clk_polarity) { RTLIL::Cell *cell = addCell(name, stringf("$_DFF_%c_", clk_polarity ? 'P' : 'N')); |