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* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-301-0/+2
| | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
* verilog: fix $past's signednessJannis Harder2022-05-251-0/+3
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* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+5
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* Next dev cycleMiodrag Milanovic2022-05-091-0/+3
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* Release version 0.17Miodrag Milanovic2022-05-091-1/+1
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* Update CHANGELOGMiodrag Milanovic2022-05-091-0/+3
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* sv: fix always_comb auto nosync for nested and function blocksZachary Snow2022-04-051-0/+4
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* Next dev cycleMiodrag Milanovic2022-04-051-0/+3
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* Release version 0.16Miodrag Milanovic2022-04-051-1/+1
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* Update CHANGELOG and manualMiodrag Milanovic2022-04-041-0/+9
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* Next dev cycleMiodrag Milanovic2022-03-041-0/+3
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* Release version 0.15Miodrag Milanovic2022-03-041-1/+1
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* Update CHANGELOGMiodrag Milanovic2022-03-021-0/+12
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* verilog: support for time scale delay valuesZachary Snow2022-02-141-0/+1
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* Fix access to whole sub-structs (#3086)Kamil Rakoczy2022-02-141-0/+3
| | | | | | * Add support for accessing whole struct * Update tests Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
* verilog: fix dynamic dynamic range asgn elabZachary Snow2022-02-111-0/+2
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* verilog: fix const func eval with upto variablesZachary Snow2022-02-111-0/+4
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* Next dev cycleMiodrag Milanovic2022-02-071-0/+3
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* Release version 0.14Miodrag Milanovic2022-02-071-1/+1
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* Update CHANGELOG and manualMiodrag Milanovic2022-02-071-0/+12
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* Next dev cycleMiodrag Milanovic2022-01-111-0/+3
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* Release version 0.13Miodrag Milanovic2022-01-111-1/+1
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* Update CHANGELOGMiodrag Milanovic2022-01-111-6/+19
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* sv: auto add nosync to certain always_comb local varsZachary Snow2022-01-071-0/+3
| | | | | If a local variable is always assigned before it is used, then adding nosync prevents latches from being needlessly generated.
* sv: fix size cast internal expression extensionZachary Snow2022-01-071-0/+2
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* sv: fix size cast clipping expression widthZachary Snow2022-01-031-0/+2
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* fix width detection of array querying function in case and case item expressionsZachary Snow2021-12-171-0/+2
| | | | | I also removed the unnecessary shadowing of `width_hint` and `sign_hint` in the corresponding case in `simplify()`.
* Next dev cycleMiodrag Milanovic2021-12-031-0/+3
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* Release version 0.12Miodrag Milanovic2021-12-031-1/+1
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* Update CHANGELOG and CODEOWNERSMiodrag Milanovic2021-12-011-0/+21
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* Next dev cycleMiodrag Milanovic2021-11-051-0/+3
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* Release version 0.11Miodrag Milanovic2021-11-051-1/+1
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* Add missing changelog itemMiodrag Milanovic2021-11-051-0/+1
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* Add missing items in CHANGELOGMiodrag Milanovic2021-10-291-0/+6
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* verilog: use derived module info to elaborate cell connectionsZachary Snow2021-10-251-0/+8
| | | | | | | | - Attempt to lookup a derived module if it potentially contains a port connection with elaboration ambiguities - Mark the cell if module has not yet been derived - This can be extended to implement automatic hierarchical port connections in a future change
* Add $aldff and $aldffe: flip-flops with async load.Marcelina Kościelnicka2021-10-021-0/+2
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* Prepare for next release cycleMiodrag Milanovic2021-09-271-1/+4
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* sv: support wand and wor of data typesZachary Snow2021-09-211-1/+2
| | | | | | This enables the usage of declarations of wand or wor with a base type of logic, integer, or a typename. Note that declarations of nets with 2-state base types is still permitted, in violation of the spec.
* Updates for CHANGELOG (#2997)Miodrag Milanović2021-09-131-48/+126
| | | Added missing changes from git log and group items
* Add v2 memory cells.Marcelina Kościelnicka2021-08-111-0/+5
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* memory: Introduce $meminit_v2 cell, with EN input.Marcelina Kościelnicka2021-07-281-0/+1
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* Replace opt_rmdff with opt_dff.Marcelina Kościelnicka2020-08-071-1/+1
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* techmap: Add _TECHMAP_CELLNAME_ special parameter.Marcelina Kościelnicka2020-07-211-1/+2
| | | | | | | This parameter will resolve to the name of the cell being mapped. The first user of this parameter will be synth_intel_alm's Quartus output, which requires a unique (and preferably descriptive) name passed as a cell parameter for the memory cells.
* Add dfflegalize pass.Marcelina Kościelnicka2020-07-011-0/+2
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* Update CHANGELOGXiretza2020-05-281-0/+1
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* Update CHANGELOG and manual for departure from upstreamEddie Hung2020-04-271-2/+2
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* select: add select -unset optionEddie Hung2020-04-161-0/+1
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* kernel: add design -delete optionEddie Hung2020-04-161-0/+1
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* Get rid of dffsr2dff.Marcelina Kościelnicka2020-04-151-0/+1
| | | | | | This pass is a proper subset of opt_rmdff, which is called by opt, which is called by every synth flow in the coarse part. Thus, it never actually does anything and can be safely removed.
* Add to changelogMiodrag Milanovic2020-02-171-0/+1
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