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| author | Zachary Snow <zach@zachjs.com> | 2021-12-15 18:15:09 -0700 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-12-17 21:22:08 -0700 |
| commit | 7608985d2c6237b869a4774c6b1659282e7473ad (patch) | |
| tree | 129bc1352eca95a6f789ef601a7f7d15ef373566 /CHANGELOG | |
| parent | 60c3ea367c942459a95e610ed98f277ce46c0142 (diff) | |
| download | yosys-7608985d2c6237b869a4774c6b1659282e7473ad.tar.gz yosys-7608985d2c6237b869a4774c6b1659282e7473ad.tar.bz2 yosys-7608985d2c6237b869a4774c6b1659282e7473ad.zip | |
fix width detection of array querying function in case and case item expressions
I also removed the unnecessary shadowing of `width_hint` and `sign_hint`
in the corresponding case in `simplify()`.
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 2 |
1 files changed, 2 insertions, 0 deletions
@@ -14,6 +14,8 @@ Yosys 0.11 .. Yosys 0.12 * SystemVerilog - Support parameters using struct as a wiretype + - Fixed regression preventing the use array querying functions in case + expressions and case item expressions * New commands and options - Added "-genlib" option to "abc" pass |