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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-27 20:54:29 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-11 13:34:10 +0200 |
| commit | fd7921776387a05edadcc90d1300670d49a73d68 (patch) | |
| tree | 84fb8ab2ff4c012b5dd24e8c3dcd5dace93474fb /CHANGELOG | |
| parent | b96eb888cc7518c20532ff688ec24b8b51f88f8e (diff) | |
| download | yosys-fd7921776387a05edadcc90d1300670d49a73d68.tar.gz yosys-fd7921776387a05edadcc90d1300670d49a73d68.tar.bz2 yosys-fd7921776387a05edadcc90d1300670d49a73d68.zip | |
Add v2 memory cells.
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -71,6 +71,11 @@ Yosys 0.9 .. Yosys 0.9-dev - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass - Merged "dffsr2dff", "opt_rmdff", "dff2dffe", "dff2dffs", "peepopt.dffmux" passes into a new "opt_dff" pass - Added $meminit_v2 cells (with support for write mask) + - Added $mem_v2, $memrd_v2, $memwr_v2, with the following features: + - write priority masks, per write/write port pair + - transparency and undefined collision behavior masks, per read/write port pair + - read port reset and initialization + - wide ports (accessing a naturally aligned power-of-two number of memory cells) Yosys 0.8 .. Yosys 0.9 ---------------------- |