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| author | Kamil Rakoczy <krakoczy@antmicro.com> | 2022-02-14 14:34:20 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-14 14:34:20 +0100 |
| commit | 68c67c40ec75b192f4f1be9711afe0df8973e797 (patch) | |
| tree | f67834903e40ae61b39a04555ff1b96763c59cd0 /CHANGELOG | |
| parent | 59738c09beb3ba43a693b77eb4545122a99df7d2 (diff) | |
| download | yosys-68c67c40ec75b192f4f1be9711afe0df8973e797.tar.gz yosys-68c67c40ec75b192f4f1be9711afe0df8973e797.tar.bz2 yosys-68c67c40ec75b192f4f1be9711afe0df8973e797.zip | |
Fix access to whole sub-structs (#3086)
* Add support for accessing whole struct
* Update tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 3 insertions, 0 deletions
@@ -11,6 +11,9 @@ Yosys 0.14 .. Yosys 0.14-dev - Fixed elaboration of dynamic range assignments where the vector is reversed or is not zero-indexed + * SystemVerilog + - Added support for accessing whole sub-structures in expressions + Yosys 0.13 .. Yosys 0.14 -------------------------- |