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| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-27 12:08:45 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-27 12:08:45 -0700 |
| commit | c34d57de2e204653cd5b550de671376f9607773b (patch) | |
| tree | a9a423d590cd88d05a060de00588a651ca0166f3 /CHANGELOG | |
| parent | a3fa9fd6e94786119c21915772fde794930c924f (diff) | |
| download | yosys-c34d57de2e204653cd5b550de671376f9607773b.tar.gz yosys-c34d57de2e204653cd5b550de671376f9607773b.tar.bz2 yosys-c34d57de2e204653cd5b550de671376f9607773b.zip | |
Update CHANGELOG and manual for departure from upstream
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -8,7 +8,7 @@ Yosys 0.9 .. Yosys 0.9-dev * Various - Added "write_xaiger" backend - - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) + - Added "abc9" pass for timing-aware techmapping (experimental, FPGA only) - Added "synth_xilinx -abc9" (experimental) - Added "synth_ice40 -abc9" (experimental) - Added "synth -abc9" (experimental) @@ -58,7 +58,6 @@ Yosys 0.9 .. Yosys 0.9-dev - Added support for SystemVerilog wildcard port connections (.*) - Added "xilinx_dffopt" pass - Added "scratchpad" pass - - Added "abc9 -dff" - Added "synth_xilinx -dff" - Improved support of $readmem[hb] Memory Content File inclusion - Added "opt_lut_ins" pass @@ -66,6 +65,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Removed "dffsr2dff" (use opt_rmdff instead) - Added "design -delete" - Added "select -unset" + - Use YosysHQ/abc instead of upstream berkeley-abc/abc Yosys 0.8 .. Yosys 0.9 ---------------------- |