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authorJannis Harder <me@jix.one>2022-05-24 17:18:53 +0200
committerZachary Snow <zachary.j.snow@gmail.com>2022-05-25 16:32:08 -0400
commitb75fa62e9b2a9f4410084fb1c80ceb23ed9d9c48 (patch)
tree3b14fe3f5d0ace0370c49b56d77fb9b2ee458f80 /CHANGELOG
parent63c9c9be5c0b0cc2b7f4588f1ac8e72eabc6bd0a (diff)
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verilog: fix $past's signedness
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diff --git a/CHANGELOG b/CHANGELOG
index ff7ce49a2..d64d592d2 100644
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+++ b/CHANGELOG
@@ -4,6 +4,9 @@ List of major changes and improvements between releases
Yosys 0.17 .. Yosys 0.17-dev
--------------------------
+ * Formal Verification
+ - Fixed the signedness of $past's return value to be the same as the
+ argument's instead of always unsigned.
* Verilog
- Fixed an issue where simplifying case statements by removing unreachable