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* Next dev cycleMiodrag Milanovic2023-04-141-0/+3
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* Release version 0.28Miodrag Milanovic2023-04-141-1/+12
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* Next dev cycleMiodrag Milanovic2023-03-061-0/+3
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* Release version 0.27Miodrag Milanovic2023-03-061-1/+12
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* Next dev cycleMiodrag Milanovic2023-02-081-0/+3
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* Release version 0.26Miodrag Milanovic2023-02-081-2/+2
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* Updated changelogMiodrag Milanovic2023-02-081-0/+18
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* Add deprecation info to changelogMiodrag Milanovic2023-01-111-0/+2
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* Next dev cycleMiodrag Milanovic2023-01-031-0/+3
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* Release version 0.25Miodrag Milanovic2023-01-031-1/+6
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* Next dev cycleMiodrag Milanovic2022-12-051-0/+3
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* Release version 0.24Miodrag Milanovic2022-12-051-1/+14
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* Merge branch 'zachjs-master'Jannis Harder2022-11-211-0/+3
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| * verilog: Support module-scoped task/function callsZachary Snow2022-10-291-0/+3
| | | | | | | | | | | | | | | | This is primarily intended to enable the standard-permitted use of module-scoped identifiers to refer to tasks and non-constant functions. As a side-effect, this also adds support for the non-standard use of module-scoped identifiers referring to constant functions, a feature that is supported in some other tools, including Iverilog.
* | Next dev cycleMiodrag Milanovic2022-11-081-0/+3
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* | Release version 0.23Miodrag Milanovic2022-11-081-1/+1
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* | Update CHANGELOGMiodrag Milanovic2022-11-071-1/+5
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* | Update CHANGELOGMiodrag Milanovic2022-11-071-0/+11
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* Add YOSYS_ABORT_ON_LOG_ERROR environment variable for debugging.Jannis Harder2022-10-071-0/+4
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* Next dev cycleMiodrag Milanovic2022-10-051-0/+3
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* Release version 0.22Miodrag Milanovic2022-10-051-1/+1
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* Update CHANGELOGMiodrag Milanovic2022-10-051-0/+8
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* Next dev cycleMiodrag Milanovic2022-09-061-0/+3
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* Release version 0.21Miodrag Milanovic2022-09-061-1/+1
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* Update ChangelogMiodrag Milanovic2022-09-061-0/+13
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* sim: -hdlname option to preserve flattened hierarchy in sim outputJannis Harder2022-08-161-0/+2
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* rename: Add -witness modeJannis Harder2022-08-161-0/+2
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* aiger: Add yosys-witness supportJannis Harder2022-08-161-0/+3
| | | | | Adds a new json based aiger map file and yosys-witness converters to us this to convert between native and AIGER witness files.
* smtbmc: Add native json based witness format + smt2 backend supportJannis Harder2022-08-161-0/+4
| | | | | | | | | | | | | | | | | | | | This adds a native json based witness trace format. By having a common format that includes everything we support, and providing a conversion utility (yosys-witness) we no longer need to implement every format for every tool that deals with witness traces, avoiding a quadratic opportunity to introduce subtle bugs. Included: * smt2: New yosys-smt2-witness info lines containing full hierarchical paths without lossy escaping. * yosys-smtbmc --dump-yw trace.yw: Dump results in the new format. * yosys-smtbmc --yw trace.yw: Read new format as constraints. * yosys-witness: New tool to convert witness formats. Currently this can only display traces in a human-readable-only format and do a passthrough read/write of the new format. * ywio.py: Small python lib for reading and writing the new format. Used by yosys-smtbmc and yosys-witness to avoid duplication.
* memory_map: Add -formal optionJannis Harder2022-08-161-0/+1
| | | | | | This maps memories for a global clock based formal verification flow. This implies -keepdc, uses $ff cells for ROMs and sets hdlname attributes.
* Add the $anyinit cell and the formalff passJannis Harder2022-08-161-0/+6
| | | | | | | These can be used to protect undefined flip-flop initialization values from optimizations that are not sound for formal verification and can help mapping all solver-provided values in witness traces for flows that use different backends simultaneously.
* Next dev cycleMiodrag Milanovic2022-08-031-0/+3
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* Release version 0.20Miodrag Milanovic2022-08-031-1/+1
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* Update ChangelogMiodrag Milanovic2022-08-031-0/+7
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* Update manual and changelogMiodrag Milanovic2022-08-031-0/+6
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* Next dev cycleMiodrag Milanovic2022-07-041-0/+3
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* Release version 0.19Miodrag Milanovic2022-07-041-1/+1
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* Mention smtlib2_module in README.md and CHANGELOGJannis Harder2022-07-041-3/+4
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* Upadte documentation and changelogMiodrag Milanovic2022-07-041-0/+15
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* Next dev cycleMiodrag Milanovic2022-06-101-0/+3
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* Release version 0.18Miodrag Milanovic2022-06-101-1/+1
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* Updated CHANGELOGMiodrag Milanovic2022-06-101-0/+3
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* verific: Added "-vlog-libext" option to specify search extension for librariesMiodrag Milanovic2022-06-091-0/+1
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* More updates on CHANGELOGMiodrag Milanovic2022-06-081-5/+9
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* Update changelog and manualMiodrag Milanovic2022-06-081-0/+10
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* verilog: fix width/sign detection for functionsZachary Snow2022-05-301-0/+2
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* verilog: fix size and signedness of array querying functionsJannis Harder2022-05-301-0/+2
| | | | | | | | | | genrtlil.cc and simplify.cc had inconsistent and slightly broken handling of signedness for array querying functions. These functions are defined to return a signed result. Simplify always produced an unsigned and genrtlil always a signed 32-bit result ignoring the context. Includes tests for the the relvant edge cases for context dependent conversions.
* verilog: fix $past's signednessJannis Harder2022-05-251-0/+3
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* verilog: fix signedness when removing unreachable casesJannis Harder2022-05-241-0/+5
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* Next dev cycleMiodrag Milanovic2022-05-091-0/+3
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