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| author | Zachary Snow <zach@zachjs.com> | 2022-02-11 22:57:31 +0100 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2022-02-14 15:58:31 +0100 |
| commit | 15a4e900b2e8f61464c7d24751b1d0182a894a1b (patch) | |
| tree | 8bfcdb75dd18e39843491429fc1e5849b70ed5b1 /CHANGELOG | |
| parent | 68c67c40ec75b192f4f1be9711afe0df8973e797 (diff) | |
| download | yosys-15a4e900b2e8f61464c7d24751b1d0182a894a1b.tar.gz yosys-15a4e900b2e8f61464c7d24751b1d0182a894a1b.tar.bz2 yosys-15a4e900b2e8f61464c7d24751b1d0182a894a1b.zip | |
verilog: support for time scale delay values
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 1 |
1 files changed, 1 insertions, 0 deletions
@@ -10,6 +10,7 @@ Yosys 0.14 .. Yosys 0.14-dev reversed dimensions - Fixed elaboration of dynamic range assignments where the vector is reversed or is not zero-indexed + - Added frontend support for time scale delay values (e.g., `#1ns`) * SystemVerilog - Added support for accessing whole sub-structures in expressions |