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| author | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-01 08:42:37 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2021-12-01 08:42:37 +0100 |
| commit | 4792d925fc89020f0ab4052bd007a0b5a426bf13 (patch) | |
| tree | 186239e28df2e2f0026271e776f56adbbdcde443 /CHANGELOG | |
| parent | 707d98b06c8d2ad196ba64afbbb3bf5af475c75b (diff) | |
| download | yosys-4792d925fc89020f0ab4052bd007a0b5a426bf13.tar.gz yosys-4792d925fc89020f0ab4052bd007a0b5a426bf13.tar.bz2 yosys-4792d925fc89020f0ab4052bd007a0b5a426bf13.zip | |
Update CHANGELOG and CODEOWNERS
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 21 |
1 files changed, 21 insertions, 0 deletions
@@ -5,6 +5,27 @@ List of major changes and improvements between releases Yosys 0.11 .. Yosys 0.11-dev -------------------------- + * Various + - Added iopadmap native support for negative-polarity output enable + - ABC update + + * SystemVerilog + - Support parameters using struct as a wiretype + + * New commands and options + - Added "-genlib" option to "abc" pass + - Added "sta" very crude static timing analysis pass + + * Verific support + - Fixed memory block size in import + + * New back-ends + - Added support for GateMate FPGA from Cologne Chip AG + + * Intel ALM support + - Added preliminary Arria V support + + Yosys 0.10 .. Yosys 0.11 -------------------------- |