verilog: use derived module info to elaborate cell connections

- Attempt to lookup a derived module if it potentially contains a port
  connection with elaboration ambiguities
- Mark the cell if module has not yet been derived
- This can be extended to implement automatic hierarchical port
  connections in a future change

1 files changed, 8 insertions, 0 deletions

diff --git a/CHANGELOG b/CHANGELOG
index a6285ddb2..b980c5a1a 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -8,6 +8,14 @@ Yosys 0.10 .. Yosys 0.10-dev
  * Various
     - Added $aldff and $aldffe (flip-flops with async load) cells
 
+ * SystemVerilog
+    - Fixed an issue which prevented writing directly to a memory word via a
+      connection to an output port
+    - Fixed an issue which prevented unbased unsized literals (e.g., `'1`) from
+      filling the width of a cell input
+    - Fixed an issue where connecting a slice covering the entirety of a signed
+      signal to a cell input would cause a failed assertion
+
 Yosys 0.9 .. Yosys 0.10
 --------------------------