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authorJannis Harder <me@jix.one>2022-05-24 14:32:14 +0200
committerZachary Snow <zachary.j.snow@gmail.com>2022-05-24 23:03:31 -0400
commitcffec1f95f0ac4bad1deb24bf7f921bd93145a16 (patch)
treec66eeb0e812b0519e8f72791c70e2b6dc44d7df3 /CHANGELOG
parentc525b5f91925bd51194ead99a4ecace313f9945c (diff)
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verilog: fix signedness when removing unreachable cases
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diff --git a/CHANGELOG b/CHANGELOG
index 4004c534b..ff7ce49a2 100644
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+++ b/CHANGELOG
@@ -5,6 +5,11 @@ List of major changes and improvements between releases
Yosys 0.17 .. Yosys 0.17-dev
--------------------------
+ * Verilog
+ - Fixed an issue where simplifying case statements by removing unreachable
+ cases could result in the wrong signedness being used for comparison with
+ the remaining cases
+
Yosys 0.16 .. Yosys 0.17
--------------------------
* New commands and options