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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-21 15:00:54 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-07-21 15:00:54 +0200 |
| commit | dc07ae96774c649d23ea787e07d618670c7e93bf (patch) | |
| tree | 04169026a40d40ca620dfa1ffc0ae6a4c04f7e8c /CHANGELOG | |
| parent | 57af8499dfc3c35d7327107ad30c1124c646fefd (diff) | |
| download | yosys-dc07ae96774c649d23ea787e07d618670c7e93bf.tar.gz yosys-dc07ae96774c649d23ea787e07d618670c7e93bf.tar.bz2 yosys-dc07ae96774c649d23ea787e07d618670c7e93bf.zip | |
techmap: Add _TECHMAP_CELLNAME_ special parameter.
This parameter will resolve to the name of the cell being mapped. The
first user of this parameter will be synth_intel_alm's Quartus output,
which requires a unique (and preferably descriptive) name passed as
a cell parameter for the memory cells.
Diffstat (limited to 'CHANGELOG')
| -rw-r--r-- | CHANGELOG | 3 |
1 files changed, 2 insertions, 1 deletions
@@ -39,7 +39,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Improvements in pmgen: slices, choices, define, generate - Added "xilinx_srl" for Xilinx shift register extraction - Removed "shregmap -tech xilinx" (superseded by "xilinx_srl") - - Added "_TECHMAP_WIREINIT_*_" attribute and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass + - Added "_TECHMAP_WIREINIT_*_" parameter and "_TECHMAP_REMOVEINIT_*_" wire for "techmap" pass - Added "-match-init" option to "dff2dffs" pass - Added "techmap_autopurge" support to techmap - Added "add -mod <modname[s]>" @@ -69,6 +69,7 @@ Yosys 0.9 .. Yosys 0.9-dev - Added $divfloor and $modfloor cells - Added $adffe, $dffsre, $sdff, $sdffe, $sdffce, $adlatch cells - Added "dfflegalize" pass + - Added "_TECHMAP_CELLNAME_" parameter for "techmap" pass Yosys 0.8 .. Yosys 0.9 ---------------------- |