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* Fixed testsMiodrag Milanovic2019-11-115-17/+34
* Do not map $eq and $ne in cmp2lut, only proper arithmetic cmpClifford Wolf2019-11-111-1/+1
* Merge pull request #1470 from YosysHQ/clifford/subpassdocClifford Wolf2019-11-101-0/+46
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| * Add CodingReadme section on script passesClifford Wolf2019-10-311-0/+46
* | Add check for valid macro names in macro definitionsClifford Wolf2019-11-071-7/+11
* | synth_xilinx: Merge blackbox primitive libraries.Marcin Kościelnicki2019-11-0611-23234/+29820
* | Fix write_aiger bug added in 524af21Clifford Wolf2019-11-041-0/+3
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* Merge pull request #1393 from whitequark/write_verilog-avoid-initClifford Wolf2019-10-271-4/+5
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| * write_verilog: do not print (*init*) attributes on regs.whitequark2019-09-221-4/+5
* | Improve naming scheme for (VHDL) modules imported from VerificClifford Wolf2019-10-241-3/+26
* | Merge pull request #1455 from YosysHQ/dave/ultrascaleplusDavid Shah2019-10-249-417/+1153
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| * | xilinx: Add URAM288 mapping for xcupDavid Shah2019-10-235-2/+92
| * | xilinx: Add support for UltraScale[+] BRAM mappingDavid Shah2019-10-237-416/+1062
* | | Add "verific -L"Clifford Wolf2019-10-241-1/+12
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* | Bugfix in smtio vcd handling of $-identifiersClifford Wolf2019-10-231-6/+9
* | xilinx: Support multiplier mapping for all families.Marcin Kościelnicki2019-10-229-9/+269
* | Merge pull request #1452 from nakengelhardt/fix_dsp_mem_regClifford Wolf2019-10-222-0/+2
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| * | Call memory_dff before DSP mapping to reserve registers (fixes #1447)N. Engelhardt2019-10-172-0/+2
* | | Add "verilog_defines -list" and "verilog_defines -reset"Clifford Wolf2019-10-211-0/+16
* | | Fix handling of "restrict" in Verific front-endClifford Wolf2019-10-211-1/+1
* | | ecp5: Pass -nomfs to abc9David Shah2019-10-201-2/+2
* | | Merge pull request #1457 from xobs/python-binary-nameMiodrag Milanović2019-10-196-9/+9
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| * | | Makefile: don't assume python is called `python3`Sean Cross2019-10-196-9/+9
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* | | Merge pull request #1454 from YosysHQ/mmicko/common_testsMiodrag Milanović2019-10-18166-1763/+455
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| * | | fixed errorMiodrag Milanovic2019-10-181-1/+1
| * | | Unify verilog styleMiodrag Milanovic2019-10-1811-191/+157
| * | | Common memory test now sharedMiodrag Milanovic2019-10-1810-89/+5
| * | | Remove not needed testsMiodrag Milanovic2019-10-184-52/+0
| * | | Share common testsMiodrag Milanovic2019-10-18103-1316/+178
| * | | fix yosys pathMiodrag Milanovic2019-10-181-2/+2
| * | | Fix path to yosysMiodrag Milanovic2019-10-185-5/+5
| * | | Moved all tests in arch sub directoryMiodrag Milanovic2019-10-18151-5/+5
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* | | Add async2syncMiodrag Milanovic2019-10-182-8/+8
* | | Merge pull request #1435 from YosysHQ/mmicko/efinixMiodrag Milanović2019-10-1827-1/+572
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| * \ \ Merge branch 'master' into mmicko/efinixMiodrag Milanović2019-10-18156-896/+3156
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* | | | Merge pull request #1434 from YosysHQ/mmicko/anlogicMiodrag Milanović2019-10-1821-0/+430
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| * \ \ \ Merge branch 'master' into mmicko/anlogicMiodrag Milanović2019-10-18136-896/+2726
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* | | | | Merge pull request #1421 from YosysHQ/eddie/pr1352Miodrag Milanović2019-10-1833-0/+669
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| * \ \ \ \ Merge branch 'master' into eddie/pr1352Miodrag Milanović2019-10-18119-987/+2470
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* | | | | | Merge pull request #1420 from YosysHQ/eddie/pr1363Miodrag Milanović2019-10-1829-47/+544
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| * | | | | hierarchy - proc reorderMiodrag Milanovic2019-10-1810-17/+21
| * | | | | Make equivalence work with latest masterMiodrag Milanovic2019-10-173-8/+8
| * | | | | remove not needed top moduleMiodrag Milanovic2019-10-172-20/+2
| * | | | | remove not needed top moduleMiodrag Milanovic2019-10-172-17/+2
| * | | | | split muxes synth per typeMiodrag Milanovic2019-10-172-39/+39
| * | | | | Test dffs separetelyMiodrag Milanovic2019-10-172-26/+19
| * | | | | Split latches into separete testsMiodrag Milanovic2019-10-172-42/+27
| * | | | | Fix formattingMiodrag Milanovic2019-10-171-1/+8
| * | | | | Clean verilog code from not used define blockMiodrag Milanovic2019-10-172-12/+0
| * | | | | Removed alu and div_mod test as agreed, ignore generated filesMiodrag Milanovic2019-10-175-70/+1
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