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* cmake: Make HeAP placer always-enabledgatecat2023-03-171-9/+1
* clangformatgatecat2023-01-251-3/+3
* Add missing <set> includesgatecat2023-01-201-0/+1
* refactor: ArcBounds -> BoundingBoxgatecat2022-12-071-1/+1
* api: Make NetInfo* of checkPipAvailForNet constgatecat2022-12-021-1/+1
* refactor: id(stringf(...)) to new idf(...) helpergatecat2022-08-101-1/+1
* Added fallback to VCC as the preferred constant if the architecture does not ...Maciej Kurc2022-05-121-1/+12
* Generalized representation of unused LUT pins connectionsMaciej Kurc2022-05-111-7/+36
* interchange: lut map cache: remove hardcoded valuesAlessandro Comodi2022-03-041-0/+9
* Switch to potentially-sparse net users arraygatecat2022-02-271-2/+2
* archapi: Use arbitrary rather than actual placement in predictDelaygatecat2021-12-191-3/+5
* Merge pull request #757 from antmicro/lut-mapping-cachegatecat2021-07-221-0/+11
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| * Added an option to disable the LUT mapping cacheMaciej Kurc2021-07-221-4/+6
| * Added more code comments, formatted the codeMaciej Kurc2021-07-221-2/+4
| * Working site LUT mapping cacheMaciej Kurc2021-07-161-0/+7
* | interchange: disallow pseudo-pip on same nets if tile has lutsAlessandro Comodi2021-07-151-8/+18
* | interchange: add constraints constraints application routineAlessandro Comodi2021-07-121-0/+1
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* interchange: Allow pseudo pip wires to overlap with bound site wires on the s...gatecat2021-07-061-8/+3
* Merge pull request #744 from YosysHQ/gatecat/const-in-macrogatecat2021-07-011-1/+1
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| * interchange: Fix handling of constants in macrosgatecat2021-07-011-1/+1
* | interchange: Reserve site ports only reachable from dedicated routinggatecat2021-07-011-0/+4
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* interchange: arch: move macro expansion step before ios packingAlessandro Comodi2021-06-181-1/+1
* Fixing old emails and names in copyrightsgatecat2021-06-121-2/+2
* interchange: add support for generating BEL clustersAlessandro Comodi2021-06-111-0/+1
* Using hashlib in archesgatecat2021-06-021-16/+3
* Use hashlib for core netlist structuresgatecat2021-06-021-2/+2
* interchange: Preliminary implementation of macro expansiongatecat2021-05-211-0/+1
* Run clangformatgatecat2021-05-161-2/+1
* interchange: site router: add valid pips list to check during routingAlessandro Comodi2021-05-131-11/+15
* interchange: arch: do not allow site pips within sitesAlessandro Comodi2021-05-121-6/+0
* interchange: Fix bounding box computationgatecat2021-05-111-2/+2
* interchange: Adding a basic global buffer placergatecat2021-05-071-0/+10
* interchange: Initial global routing implementationgatecat2021-05-071-0/+20
* interchange: Implement getWireTypegatecat2021-04-301-1/+18
* interchange: Handle disconnected/missing cell pinsgatecat2021-04-191-0/+53
* clangformatgatecat2021-04-121-9/+10
* interchange: Disambiguate cell and bel pins when creating Vcc tiesgatecat2021-04-091-6/+10
* [interchange] Provide estimateDelay when USE_LOOKAHEAD is not defined.Keith Rothman2021-04-061-1/+16
* [interchange] Remove requirement to have wire_lut.Keith Rothman2021-04-061-6/+0
* [interchange] Scale edge cost of pseudo pips.Keith Rothman2021-04-061-0/+11
* [interchange] Disallow site edges during general routing.Keith Rothman2021-04-061-5/+22
* [interchange] Add crude pseudo pip model.Keith Rothman2021-04-061-4/+35
* [interchange] Update to v6 of FPGA interchange chipdb.Keith Rothman2021-04-011-1/+6
* [interchange] Fix site pip check for drivers.Keith Rothman2021-03-301-7/+22
* Implement debugging tools for site router.Keith Rothman2021-03-251-0/+30
* Re-work LUT mapping logic to only put VCC pins when required.Keith Rothman2021-03-251-98/+35
* Fixup some of the re-mapping logic.Keith Rothman2021-03-251-24/+74
* Add initial handling of local site inverters and constant signals.Keith Rothman2021-03-251-20/+95
* Merge pull request #643 from litghost/id_constantsgatecat2021-03-231-4/+25
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| * [FPGA interchange] Convert some string constants to IdString.Keith Rothman2021-03-231-4/+25
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