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author | Alessandro Comodi <acomodi@antmicro.com> | 2022-03-04 16:53:03 +0100 |
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committer | Alessandro Comodi <acomodi@antmicro.com> | 2022-03-04 16:53:24 +0100 |
commit | b5d6fc8ed7bc446b1d810c82029e7b327bea5049 (patch) | |
tree | 1ea2dc8c8037d46c22cc72dad0a8f2272621ee75 /fpga_interchange/arch.cc | |
parent | 2c6ca4836fd30faa5cdbd931a352866e5a04104d (diff) | |
download | nextpnr-b5d6fc8ed7bc446b1d810c82029e7b327bea5049.tar.gz nextpnr-b5d6fc8ed7bc446b1d810c82029e7b327bea5049.tar.bz2 nextpnr-b5d6fc8ed7bc446b1d810c82029e7b327bea5049.zip |
interchange: lut map cache: remove hardcoded values
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r-- | fpga_interchange/arch.cc | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index a5e802d3..e55c94af 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -224,10 +224,14 @@ Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false) // Initially LutElement vectors for each tile type. tile_type_index = 0; + max_lut_cells = 0; + max_lut_pins = 0; lut_elements.resize(chip_info->tile_types.size()); for (const TileTypeInfoPOD &tile_type : chip_info->tile_types) { std::vector<LutElement> &elements = lut_elements[tile_type_index++]; elements.reserve(tile_type.lut_elements.size()); + + int lut_cells_count = 0; for (auto &lut_element : tile_type.lut_elements) { elements.emplace_back(); @@ -252,10 +256,15 @@ Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false) } lut.output_pin = IdString(lut_bel.out_pin); + lut_cells_count++; + + max_lut_pins = std::max((int)lut_bel.pins.size(), max_lut_pins); } element.compute_pin_order(); } + + max_lut_cells = std::max(lut_cells_count, max_lut_cells); } // Map lut cell types to their LutCellPOD |