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authorKeith Rothman <537074+litghost@users.noreply.github.com>2021-03-23 09:37:22 -0700
committerKeith Rothman <537074+litghost@users.noreply.github.com>2021-03-23 09:38:37 -0700
commit0dd93035e449d40eaab7172546bfc73495e798d7 (patch)
treec9f8155251c011d3a5973c7c66855eef88c3a9a1 /fpga_interchange/arch.cc
parentb7bf2c706fcb24242b93b1993c8073d82d4028bb (diff)
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[FPGA interchange] Convert some string constants to IdString.
Also add some optional diagnostic prints for cell -> BEL pin mapping. Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r--fpga_interchange/arch.cc29
1 files changed, 25 insertions, 4 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 476801aa..d3bc9b40 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -131,6 +131,9 @@ Arch::Arch(ArchArgs args) : args(args)
IdString::initialize_add(this, constids[i].get(), i + 1);
}
+ id_GND = id("GND");
+ id_VCC = id("VCC");
+
// Sanity check cell name ids.
const CellMapPOD &cell_map = *chip_info->cell_map;
int32_t first_cell_id = cell_map.cell_names[0];
@@ -1046,7 +1049,7 @@ void Arch::map_cell_pins(CellInfo *cell, int32_t mapping, bool bind_constants)
continue;
}
- if (cell_pin.str(this) == "GND") {
+ if (cell_pin == id_GND) {
if (bind_constants) {
PortInfo port_info;
port_info.name = bel_pin;
@@ -1068,7 +1071,7 @@ void Arch::map_cell_pins(CellInfo *cell, int32_t mapping, bool bind_constants)
continue;
}
- if (cell_pin.str(this) == "VCC") {
+ if (cell_pin == id_VCC) {
if (bind_constants) {
PortInfo port_info;
port_info.name = bel_pin;
@@ -1106,16 +1109,23 @@ void Arch::map_cell_pins(CellInfo *cell, int32_t mapping, bool bind_constants)
continue;
}
+#ifdef DEBUG_CELL_PIN_MAPPING
+ log_info("parameter match on param_key %s\n", param_key.c_str(this));
+#endif
+
for (const auto &pin_map : parameter_pin_map.pins) {
IdString cell_pin(pin_map.cell_pin);
IdString bel_pin(pin_map.bel_pin);
+#ifdef DEBUG_CELL_PIN_MAPPING
+ log_info(" %s => %s\n", cell_pin.c_str(this), bel_pin.c_str(this));
+#endif
// Skip assigned LUT pins, as they are already mapped!
if (cell->lut_cell.lut_pins.count(cell_pin) && cell->cell_bel_pins.count(cell_pin)) {
continue;
}
- if (cell_pin.str(this) == "GND") {
+ if (cell_pin == id_GND) {
if (bind_constants) {
PortInfo port_info;
port_info.name = bel_pin;
@@ -1137,7 +1147,7 @@ void Arch::map_cell_pins(CellInfo *cell, int32_t mapping, bool bind_constants)
continue;
}
- if (cell_pin.str(this) == "VCC") {
+ if (cell_pin == id_VCC) {
if (bind_constants) {
PortInfo port_info;
port_info.name = bel_pin;
@@ -1162,6 +1172,17 @@ void Arch::map_cell_pins(CellInfo *cell, int32_t mapping, bool bind_constants)
cell->cell_bel_pins[cell_pin].push_back(bel_pin);
}
}
+
+#ifdef DEBUG_CELL_PIN_MAPPING
+ log_info("Pin mapping for cell %s (type: %s)\n", cell->name.c_str(getCtx()), cell->type.c_str(getCtx()));
+ for (auto &pin_pair : cell->cell_bel_pins) {
+ log_info(" %s =>", pin_pair.first.c_str(getCtx()));
+ for (IdString bel_pin : pin_pair.second) {
+ log(" %s", bel_pin.c_str(getCtx()));
+ }
+ log("\n");
+ }
+#endif
}
void Arch::map_port_pins(BelId bel, CellInfo *cell) const