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authorgatecat <gatecat@ds0.me>2021-04-30 11:07:31 +0100
committergatecat <gatecat@ds0.me>2021-04-30 11:07:31 +0100
commitdcb09ec8deddb1c90c53acc157baf941fb875142 (patch)
tree72c6edcd4da343337b2ab9e3e8bd36921320d9a4 /fpga_interchange/arch.cc
parentecf24201ec35c01045a970cff4ed471f1b23a19b (diff)
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interchange: Implement getWireType
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r--fpga_interchange/arch.cc19
1 files changed, 18 insertions, 1 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 441c2e1f..c49a172b 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -461,7 +461,24 @@ WireId Arch::getWireByName(IdStringList name) const
return ret;
}
-IdString Arch::getWireType(WireId wire) const { return id(""); }
+IdString Arch::getWireType(WireId wire) const
+{
+ int tile = wire.tile, index = wire.index;
+ if (tile == -1) {
+ // Nodal wire
+ const TileWireRefPOD &wr = chip_info->nodes[wire.index].tile_wires[0];
+ tile = wr.tile;
+ index = wr.index;
+ }
+ auto &w2t = chip_info->tiles[tile].tile_wire_to_type;
+ if (index >= w2t.ssize())
+ return IdString();
+ int wire_type = w2t[index];
+ if (wire_type == -1)
+ return IdString();
+ return IdString(chip_info->wire_types[wire_type].name);
+}
+
std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) const { return {}; }
// -----------------------------------------------------------------------