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authorgatecat <gatecat@ds0.me>2021-07-22 14:09:40 +0100
committerGitHub <noreply@github.com>2021-07-22 14:09:40 +0100
commit5212e38512586a6aea0a3b075d30cd172026cd3e (patch)
tree9ea2c4a1091424cd131e8fdab67a4f9339213894 /fpga_interchange/arch.cc
parent8733cce5fa44e095e654f487781555bd20edc48f (diff)
parent580a45485afe48a77272f44f8aa99875cdd4d441 (diff)
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Merge pull request #757 from antmicro/lut-mapping-cache
interchange: Add caching of site LUT mapping solution
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r--fpga_interchange/arch.cc11
1 files changed, 11 insertions, 0 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index d67f54fd..a39f49e6 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -814,6 +814,14 @@ bool Arch::place()
getCtx()->attrs[getCtx()->id("step")] = std::string("place");
archInfoToAttributes();
+ // Print site LUT mapping caching stats
+ if (!getCtx()->arch_args.disable_lut_mapping_cache) {
+ log_info("Site LUT mapping cache stats:\n");
+ log_info(" miss ratio: %.1f%%\n", getCtx()->site_lut_mapping_cache.getMissRatio() * 100.0f);
+ log_info(" peak size : %zuMB (%zu items)\n", getCtx()->site_lut_mapping_cache.getSizeMB(),
+ getCtx()->site_lut_mapping_cache.getCount());
+ }
+
getCtx()->check();
return true;
@@ -837,6 +845,9 @@ static void prepare_sites_for_routing(Context *ctx)
// pins to ensure a routeable pin choice.
ctx->site_routing_cache.clear();
+ // Clear the LUT mapping cache
+ ctx->site_lut_mapping_cache.clear();
+
// Have site router bind site routing (via bindPip and bindWire).
// This is important so that the pseudo pips are correctly blocked prior
// to handing the design to the generalized router algorithms.