[interchange] Update to v6 of FPGA interchange chipdb.

Changes:
 - Adds LUT output pin to LutBelPOD.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 2e1c452a..0d6cc4de 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -247,10 +247,13 @@ Arch::Arch(ArchArgs args) : args(args)
             LutElement &element = elements.back();
             element.width = lut_element.width;
             for (auto &lut_bel : lut_element.lut_bels) {
-                auto result = element.lut_bels.emplace(IdString(lut_bel.name), LutBel());
+                IdString name(lut_bel.name);
+                auto result = element.lut_bels.emplace(name, LutBel());
                 NPNR_ASSERT(result.second);
                 LutBel &lut = result.first->second;
 
+                lut.name = name;
+
                 lut.low_bit = lut_bel.low_bit;
                 lut.high_bit = lut_bel.high_bit;
 
@@ -260,6 +263,8 @@ Arch::Arch(ArchArgs args) : args(args)
                     lut.pins.push_back(pin);
                     lut.pin_to_index[pin] = i;
                 }
+
+                lut.output_pin = IdString(lut_bel.out_pin);
             }
 
             element.compute_pin_order();