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authorMaciej Kurc <mkurc@antmicro.com>2021-07-16 16:01:21 +0200
committerMaciej Kurc <mkurc@antmicro.com>2021-07-22 12:59:10 +0200
commit8fc16a57c9dee5e7e0f83752a62612f70f18a38e (patch)
treeac90d66d237215ef241bb05dd2781948bc8f4a75 /fpga_interchange/arch.cc
parentccf2bb123c4c2f52142c82c3b6338856df4fbb80 (diff)
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Added more code comments, formatted the code
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r--fpga_interchange/arch.cc6
1 files changed, 4 insertions, 2 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index 33720e98..64eef2ad 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -814,8 +814,10 @@ bool Arch::place()
archInfoToAttributes();
// Print site LUT mapping caching stats
- log_info("Site LUT mapping cache miss ratio: %.1f%%\n",
- getCtx()->site_lut_mapping_cache.getMissRatio() * 100.0f);
+ log_info("Site LUT mapping cache stats:\n");
+ log_info(" miss ratio: %.1f%%\n", getCtx()->site_lut_mapping_cache.getMissRatio() * 100.0f);
+ log_info(" peak size : %zuMB (%zu items)\n", getCtx()->site_lut_mapping_cache.getSizeMB(),
+ getCtx()->site_lut_mapping_cache.getCount());
getCtx()->check();