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authorgatecat <gatecat@ds0.me>2021-04-09 10:23:56 +0100
committergatecat <gatecat@ds0.me>2021-04-09 10:26:32 +0100
commit93e34b8754d96d3f4ffeddad9b3baf5d5cb378b0 (patch)
treee6dde27f493acf1f76b8be8c438ba6aa09147318 /fpga_interchange/arch.cc
parent581682a08e6113eb8abfaf9e690e399e350e982c (diff)
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interchange: Disambiguate cell and bel pins when creating Vcc ties
The pins created for tieing to Vcc were being named after the bel pin, relying on the fact that Xilinx names cell and bel pins differently for LUTs. This isn't true for Nexus devices which uses the same names for both, and was causing a failure as a result. This uses a "PHYS_" prefix that's highly unlikely to appear in a cell pin name to disambiguate. Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/arch.cc')
-rw-r--r--fpga_interchange/arch.cc16
1 files changed, 10 insertions, 6 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc
index aab73b4d..e468d194 100644
--- a/fpga_interchange/arch.cc
+++ b/fpga_interchange/arch.cc
@@ -826,8 +826,12 @@ static void prepare_sites_for_routing(Context *ctx)
}
for (auto bel_pin : cell->lut_cell.vcc_pins) {
+ // We can't rely on bel pins not clashing with cell names (for Xilinx they use different naming schemes, for
+ // Nexus they are the same) so add a prefix to the bel pin name to disambiguate it
+ IdString cell_pin = ctx->id(stringf("%s_PHYS", ctx->nameOf(bel_pin)));
+
PortInfo port_info;
- port_info.name = bel_pin;
+ port_info.name = cell_pin;
port_info.type = PORT_IN;
port_info.net = nullptr;
@@ -837,14 +841,14 @@ static void prepare_sites_for_routing(Context *ctx)
}
#endif
- auto result = cell->ports.emplace(bel_pin, port_info);
+ auto result = cell->ports.emplace(cell_pin, port_info);
if (result.second) {
- cell->cell_bel_pins[bel_pin].push_back(bel_pin);
- ctx->connectPort(vcc_net_name, cell->name, bel_pin);
- cell->const_ports.emplace(bel_pin);
+ cell->cell_bel_pins[cell_pin].push_back(bel_pin);
+ ctx->connectPort(vcc_net_name, cell->name, cell_pin);
+ cell->const_ports.emplace(cell_pin);
} else {
NPNR_ASSERT(result.first->second.net == ctx->getNetByAlias(vcc_net_name));
- auto result2 = cell->cell_bel_pins.emplace(bel_pin, std::vector<IdString>({bel_pin}));
+ auto result2 = cell->cell_bel_pins.emplace(cell_pin, std::vector<IdString>({bel_pin}));
NPNR_ASSERT(result2.first->second.at(0) == bel_pin);
NPNR_ASSERT(result2.first->second.size() == 1);
}