iCE40/nextpnr - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
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* \|	Initial version of inverter logic.	Keith Rothman	2021-03-23	1	-0/+31
* \|	Use new parameter definition data in FPGA interchange processing.	Keith Rothman	2021-03-23	1	-41/+5
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*	Initial lookahead for FPGA interchange.	Keith Rothman	2021-03-23	1	-13/+39
*	Merge pull request #637 from litghost/refine_site_router	gatecat	2021-03-22	1	-2/+30
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\| *	Rework FPGA interchange site router.	Keith Rothman	2021-03-22	1	-2/+30
* \|	Add "checkPipAvailForNet" to Arch API.	Keith Rothman	2021-03-22	1	-2/+2
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*	Add pseudo pip data to chipdb (with schema bump).	Keith Rothman	2021-03-22	1	-5/+127
*	Refactor header structures in FPGA interchange Arch.	Keith Rothman	2021-03-19	1	-9/+285
*	Use NEXTPNR_NAMESPACE macro's now that headers are seperated.	Keith Rothman	2021-03-15	1	-1/+1
*	clangformat	gatecat	2021-03-03	1	-1/+2
*	Initial LUT rotation logic.	Keith Rothman	2021-02-26	1	-1/+196
*	Fix assorted bugs in FPGA interchange.	Keith Rothman	2021-02-23	1	-85/+158
*	Finish dedicated interconnect implementation.	Keith Rothman	2021-02-23	1	-9/+36
*	Working FF example now that constant merging is done.	Keith Rothman	2021-02-23	1	-5/+182
*	Add initial logic for handling dedicated interconnect situations.	Keith Rothman	2021-02-23	1	-0/+5
*	Remove some signedness warnings.	Keith Rothman	2021-02-23	1	-1/+1
*	Add initial constant network support to FPGA interchange arch.	Keith Rothman	2021-02-23	1	-1/+1
*	Replace DelayInfo with DelayPair/DelayQuad	gatecat	2021-02-19	1	-1/+1
*	Add some utility methods for site instance access.	Keith Rothman	2021-02-18	1	-2/+2
*	Refactor "get only from iterator" to a utility.	Keith Rothman	2021-02-17	1	-5/+2
*	Change how package pin IO sites are selected.	Keith Rothman	2021-02-17	1	-1/+17
*	Continue fixes.	Keith Rothman	2021-02-17	1	-0/+12
*	Add initial site router.	Keith Rothman	2021-02-17	1	-1/+1
*	Working on standing up initial constraints system.	Keith Rothman	2021-02-17	1	-11/+76
*	clangformat	gatecat	2021-02-17	1	-3/+4
*	Require `--package` when arch BBA contains multiple packages.	Keith Rothman	2021-02-16	1	-3/+11
*	[FPGA Interchange] Add Cell -> BEL Pin maps.	Keith Rothman	2021-02-16	1	-7/+161
*	Add FPGA interchange frontend and backend.	Keith Rothman	2021-02-15	1	-2/+19
*	Run "make clangformat".	Keith Rothman	2021-02-12	1	-5/+5
*	Refactor XDC parser into a little class for testing purposes.	Keith Rothman	2021-02-12	1	-0/+11
*	Add FPGA interchange XDC parser.	Keith Rothman	2021-02-12	1	-0/+7
*	interchange: Base on ArchAPI	D. Shah	2021-02-08	1	-3/+1
*	Add RelSlice::ssize and use it when comparing with signed ints.	Keith Rothman	2021-02-05	1	-14/+14
*	Move all string data into BBA file.	Keith Rothman	2021-02-05	1	-8/+8
*	Use RelSlice instead of RelPtr in cases where sizes are present.	Keith Rothman	2021-02-04	1	-17/+17
*	Update APIs to conform to style guide.	Keith Rothman	2021-02-04	1	-10/+10
*	Update copywrite headers.	Keith Rothman	2021-02-04	1	-1/+2
*	Fix warnings with signed/unsigned.	Keith Rothman	2021-02-04	1	-1/+1
*	Run "make clangformat".	Keith Rothman	2021-02-04	1	-36/+23
*	Update FPGA interchange to use IdStringList.	Keith Rothman	2021-02-04	1	-100/+112
*	Start adding data for placement constraint solving.	Keith Rothman	2021-02-04	1	-45/+21
*	Add initial updates to FPGA interchange arch for BEL buckets.	Keith Rothman	2021-02-04	1	-0/+7
*	Address review comments.	Keith Rothman	2021-02-04	1	-8/+5
*	Fix BBA import bugs.	Keith Rothman	2021-02-04	1	-48/+155
*	Assorted fixes to new FPGA interchange based arch.	Keith Rothman	2021-02-04	1	-4/+12
*	Initial compiling version.	Keith Rothman	2021-02-04	1	-0/+9
*	Initial FPGA interchange (which is just a cut-down xilinx arch).	Keith Rothman	2021-02-04	1	-0/+474