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| author | gatecat <gatecat@ds0.me> | 2021-07-01 11:08:36 +0100 |
|---|---|---|
| committer | gatecat <gatecat@ds0.me> | 2021-07-01 11:28:12 +0100 |
| commit | 523ffbaa37a367557da434752cb286643e24b627 (patch) | |
| tree | e84b3942906526958d223f7d62b53f62571c82d7 /fpga_interchange/arch.cc | |
| parent | 2124da44d87353dd0c7b0d2bf57ddf7789d9c39c (diff) | |
| download | nextpnr-523ffbaa37a367557da434752cb286643e24b627.tar.gz nextpnr-523ffbaa37a367557da434752cb286643e24b627.tar.bz2 nextpnr-523ffbaa37a367557da434752cb286643e24b627.zip | |
interchange: Reserve site ports only reachable from dedicated routing
Signed-off-by: gatecat <gatecat@ds0.me>
Diffstat (limited to 'fpga_interchange/arch.cc')
| -rw-r--r-- | fpga_interchange/arch.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index de172d90..e9bc4559 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -832,6 +832,10 @@ static void prepare_sites_for_routing(Context *ctx) } } + // Clear the site routing cache. This is because routing at this stage is done with the extra constraint of blocked + // pins to ensure a routeable pin choice. + ctx->site_routing_cache.clear(); + // Have site router bind site routing (via bindPip and bindWire). // This is important so that the pseudo pips are correctly blocked prior // to handing the design to the generalized router algorithms. |