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| author | Maciej Kurc <mkurc@antmicro.com> | 2021-07-09 15:40:06 +0200 |
|---|---|---|
| committer | Maciej Kurc <mkurc@antmicro.com> | 2021-07-16 12:51:28 +0200 |
| commit | d52516756cf32ecb53b75e8a6f032ebeeb427a71 (patch) | |
| tree | 177e69eab87605db020a66ae1cf5a0494e6c9151 /fpga_interchange/arch.cc | |
| parent | c696e885736ed052bd1d5e8fd91b42ee3bc6af9f (diff) | |
| download | nextpnr-d52516756cf32ecb53b75e8a6f032ebeeb427a71.tar.gz nextpnr-d52516756cf32ecb53b75e8a6f032ebeeb427a71.tar.bz2 nextpnr-d52516756cf32ecb53b75e8a6f032ebeeb427a71.zip | |
Working site LUT mapping cache
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'fpga_interchange/arch.cc')
| -rw-r--r-- | fpga_interchange/arch.cc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/fpga_interchange/arch.cc b/fpga_interchange/arch.cc index 901725d4..33720e98 100644 --- a/fpga_interchange/arch.cc +++ b/fpga_interchange/arch.cc @@ -813,6 +813,10 @@ bool Arch::place() getCtx()->attrs[getCtx()->id("step")] = std::string("place"); archInfoToAttributes(); + // Print site LUT mapping caching stats + log_info("Site LUT mapping cache miss ratio: %.1f%%\n", + getCtx()->site_lut_mapping_cache.getMissRatio() * 100.0f); + getCtx()->check(); return true; @@ -836,6 +840,9 @@ static void prepare_sites_for_routing(Context *ctx) // pins to ensure a routeable pin choice. ctx->site_routing_cache.clear(); + // Clear the LUT mapping cache + ctx->site_lut_mapping_cache.clear(); + // Have site router bind site routing (via bindPip and bindWire). // This is important so that the pseudo pips are correctly blocked prior // to handing the design to the generalized router algorithms. |