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* Merge pull request #1648 from YosysHQ/eddie/cmp2lcuEddie Hung2020-04-031-0/+52
|\ | | | | "techmap -map +/cmp2lcu.v" for decomposing arithmetic compares to $lcu
| * +/cmp2lcu.v to work efficiently for fully/partially constant inputsEddie Hung2020-04-031-3/+31
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| * Refactor +/cmp2lcu.v into recursive techmapEddie Hung2020-04-031-1/+1
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| * techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcuEddie Hung2020-04-031-0/+24
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* | iopadmap: Fix z assignment to inout portMarcin Kościelnicki2020-04-021-1/+9
|/ | | | Fixes #1841.
* Merge pull request #1790 from YosysHQ/eddie/opt_expr_xorEddie Hung2020-04-013-7/+55
|\ | | | | opt_expr: optimise $xor/$xnor/$_XOR_/$_XNOR_ -s with constant inputs
| * opt_expr: add failing $xnor testEddie Hung2020-03-201-1/+13
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| * Simplify breaking tests/arch/*/fsm.ys testsEddie Hung2020-03-202-7/+3
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| * opt_expr: add $xor/$xnor/$_XOR_/$_XNOR_ testsEddie Hung2020-03-191-0/+40
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* | Merge pull request #1789 from YosysHQ/eddie/opt_expr_aluEddie Hung2020-04-011-0/+63
|\ \ | | | | | | opt_expr: improve performance on $alu and $sub
| * | opt_expr: add $alu testsEddie Hung2020-03-191-0/+63
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* | Merge pull request #1848 from YosysHQ/eddie/fix_dynsliceClaire Wolf2020-04-011-0/+12
|\ \ | | | | | | ast: simplify to fully populate dynamic slicing case transformation
| * | Add dynamic slicing Verilog testcaseEddie Hung2020-03-311-0/+12
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* | Merge pull request #1761 from YosysHQ/eddie/opt_merge_speedupEddie Hung2020-03-312-0/+92
|\ \ | | | | | | opt_merge: speedup
| * | opt_merge: speedupEddie Hung2020-03-162-0/+92
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* | Merge pull request #1811 from PeterCrozier/typedef_scopeN. Engelhardt2020-03-301-0/+7
|\ \ | | | | | | Support module/package/interface/block scope for typedef names.
| * | Support module/package/interface/block scope for typedef names.Peter Crozier2020-03-231-0/+7
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* | | Add support for SystemVerilog-style `define to Verilog frontendRupert Swarbrick2020-03-274-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch should support things like `define foo(a, b = 3, c) a+b+c `foo(1, ,2) which will evaluate to 1+3+2. It also spots mistakes like `foo(1) (the 3rd argument doesn't have a default value, so a call site is required to set it). Most of the patch is a simple parser for the format in preproc.cc, but I've also taken the opportunity to wrap up the "name -> definition" map in a type, rather than use multiple std::map's. Since this type needs to be visible to code that touches defines, I've pulled it (and the frontend_verilog_preproc declaration) out into a new file at frontends/verilog/preproc.h and included that where necessary. Finally, the patch adds a few tests in tests/various to check that we are parsing everything correctly.
* | | Merge pull request #1806 from YosysHQ/mwk/techmap-replace-fixClaire Wolf2020-03-261-0/+18
|\ \ \ | | | | | | | | techmap: Fix cell names with _TECHMAP_REPLACE_.*
| * | | techmap: Fix cell names with _TECHMAP_REPLACE_.*Marcin Kościelnicki2020-03-231-0/+18
| | | | | | | | | | | | | | | | Fixes #1804.
* | | | Merge pull request #1763 from boqwxp/issue1762N. Engelhardt2020-03-235-0/+19
|\ \ \ \ | |_|/ / |/| | | Closes #1762. Adds warnings for `select` arguments not matching any object and for `add` command when no modules selected
| * | | Do not warn on empty selection with prefixed `arg_memb`.Alberto Gonzalez2020-03-231-0/+5
| | | | | | | | | | | | | | | | Co-Authored-By: N. Engelhardt <nak@symbioticeda.com>
| * | | Suppress warnings for empty `select` arguments when `-count` or `-assert-*` ↵Alberto Gonzalez2020-03-231-0/+2
| | | | | | | | | | | | | | | | options are set.
| * | | Add tests for `select` command warnings.Alberto Gonzalez2020-03-233-0/+12
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* | | | Merge pull request #1803 from Grazfather/typedefN. Engelhardt2020-03-237-25/+26
|\ \ \ \ | |_|/ / |/| | | Support standard typedef grammar (Fixed)
| * | | Revert typedef tests to standard grammar.Peter2020-03-227-25/+26
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* | | | Add test for abc9+mince issueDavid Shah2020-03-201-0/+17
|/ / / | | | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | | fsm_extract: Initialize celltypes with full design.Marcin Kościelnicki2020-03-191-0/+33
| | | | | | | | | | | | Fixes #1781.
* | | Merge pull request #1774 from boqwxp/execN. Engelhardt2020-03-191-0/+6
|\ \ \ | | | | | | | | Add `exec` command to allow running shell commands from inside Yosys scripts
| * | | Add test for `exec` command.Alberto Gonzalez2020-03-161-0/+6
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* / / fix argument order for macOS compatibilityN. Engelhardt2020-03-181-3/+3
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* | Merge pull request #1759 from zeldin/constant_with_comment_reduxMiodrag Milanović2020-03-142-0/+24
|\ \ | | | | | | refixed parsing of constant with comment between size and value
| * | Add regression tests for new handling of comments in constantsMarcus Comstedt2020-03-142-0/+24
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* | Merge pull request #1754 from boqwxp/precise_locationsMiodrag Milanović2020-03-141-0/+8
|\ \ | | | | | | Set AST node source location in more parser rules.
| * | verilog: add testEddie Hung2020-03-111-0/+8
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* | | Added back tests for loggerMiodrag Milanovic2020-03-134-0/+24
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* | Merge pull request #1721 from YosysHQ/dave/tribuf-unusedDavid Shah2020-03-101-0/+14
|\ \ | |/ |/| deminout: Don't demote inouts with unused bits
| * deminout: Don't demote inouts with unused bitsDavid Shah2020-03-041-0/+14
| | | | | | | | Signed-off-by: David Shah <dave@ds0.me>
* | Fix partsel expr bit width handling and add test caseClaire Wolf2020-03-081-0/+4
| | | | | | | | Signed-off-by: Claire Wolf <claire@symbioticeda.com>
* | rpc test: make frontend listen before launching yosys & introduce safeguard ↵N. Engelhardt2020-03-061-1/+2
| | | | | | | | if yosys errors
* | tests: extend tests/arch/run-tests.sh for definesEddie Hung2020-03-051-3/+14
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* | Merge pull request #1718 from boqwxp/precise_locationsClaire Wolf2020-03-032-4/+4
|\ \ | | | | | | Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
| * | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| | | | | | | | | | | | line number.
| * | Change attribute search value to specify precise location instead of simple ↵Alberto Gonzalez2020-02-241-2/+2
| |/ | | | | | | line number.
* | Merge pull request #1519 from YosysHQ/eddie/submod_poClaire Wolf2020-03-031-0/+124
|\ \ | | | | | | submod: several bugfixes
| * \ Merge branch 'master' into eddie/submod_poEddie Hung2020-02-0183-175/+2399
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| * | | Add a quick testcase for unknown modules as inoutEddie Hung2019-12-091-2/+24
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* | | | iopadmap: Look harder for already-present buffers. (#1731)Marcelina Kościelnicka2020-03-021-2/+21
| | | | | | | | | | | | | | | | | | | | iopadmap: Look harder for already-present buffers. Fixes #1720.
* | | | Merge pull request #1724 from YosysHQ/eddie/abc9_specifyEddie Hung2020-03-026-7/+10
|\ \ \ \ | | | | | | | | | | abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
| * | | | Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"Eddie Hung2020-02-271-3/+9
| | | | | | | | | | | | | | | | | | | | This reverts commit 68f903c6dd7403a4cf280cf71ee02d20345938b5.
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