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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 14:38:50 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-20 14:38:50 -0700 |
| commit | 6274f0b075abba2af9193e2245eacee5cc66e4c5 (patch) | |
| tree | d72e5311030b55d37fdb1d891a2875e834e25135 /tests | |
| parent | 317c18fc6fe22f6b5ad4f0ac82f6abbcfaec2bca (diff) | |
| download | yosys-6274f0b075abba2af9193e2245eacee5cc66e4c5.tar.gz yosys-6274f0b075abba2af9193e2245eacee5cc66e4c5.tar.bz2 yosys-6274f0b075abba2af9193e2245eacee5cc66e4c5.zip | |
opt_expr: add failing $xnor test
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_expr_xor.ys | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/tests/opt/opt_expr_xor.ys b/tests/opt/opt_expr_xor.ys index a458c9a27..21439fd53 100644 --- a/tests/opt/opt_expr_xor.ys +++ b/tests/opt/opt_expr_xor.ys @@ -14,7 +14,7 @@ equiv_opt opt_expr design -load postopt select -assert-none t:$xor select -assert-none t:$xnor -select -assert-count 2 t:$_NOT_ +select -assert-count 2 t:$not design -load read @@ -38,3 +38,15 @@ equiv_opt opt_expr design -load postopt select -assert-none t:$_XNOR_ # NB: simplemap does $xnor -> $_XOR_+$_NOT_ select -assert-count 1 t:$_NOT_ + + +design -reset +read_verilog <<EOT +module top(input a, output [1:0] w, x, y, z); +assign w = a^1'b0; +assign x = a^1'b1; +assign y = a~^1'b0; +assign z = a~^1'b1; +endmodule +EOT +equiv_opt opt_expr |