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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-17 10:51:27 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-03 14:28:22 -0700 |
| commit | 9b6370067858aa37825e7a030cd204726f0b58f9 (patch) | |
| tree | 4617b57873d6c2bebe6a1333e794fd3a96cb7b1f /tests | |
| parent | fffe42d4c1dbfdf976ecb84e16a759552c8e2dd0 (diff) | |
| download | yosys-9b6370067858aa37825e7a030cd204726f0b58f9.tar.gz yosys-9b6370067858aa37825e7a030cd204726f0b58f9.tar.bz2 yosys-9b6370067858aa37825e7a030cd204726f0b58f9.zip | |
techmap +/cmp2lcu.v for decomposing arithmetic compares to $lcu
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/cmp2lcu.ys | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys new file mode 100644 index 000000000..e7a422e2f --- /dev/null +++ b/tests/techmap/cmp2lcu.ys @@ -0,0 +1,24 @@ +read_verilog <<EOT +module top(input [11:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les); +assign gtu = a > b; +assign gts = $signed(a) > $signed(b); +assign ltu = a < b; +assign lts = $signed(a) < $signed(b); +assign geu = a >= b; +assign ges = $signed(a) >= $signed(b); +assign leu = a <= b; +assign les = $signed(a) <= $signed(b); +endmodule +EOT +proc + +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=6 +design -load postopt +select -assert-count 8 t:$lcu +select -assert-none t:$gt t:$ge t:$lt t:$le + +design -load preopt +equiv_opt -assert techmap -map +/cmp2lcu.v -D LUT_WIDTH=4 +design -load postopt +select -assert-count 8 t:$lcu +select -assert-none t:$gt t:$ge t:$lt t:$le |