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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 14:57:10 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-19 14:57:10 -0700 |
| commit | 5e2562f1a2e4cfa53c80f9ca6200aecc4cc6fd9b (patch) | |
| tree | e67ca7d22c47a1f8afb3c8565b43c045d022e9cb /tests | |
| parent | 8d1fa0e3b91c9439d2ab1e24c29b7ccdfcc91606 (diff) | |
| download | yosys-5e2562f1a2e4cfa53c80f9ca6200aecc4cc6fd9b.tar.gz yosys-5e2562f1a2e4cfa53c80f9ca6200aecc4cc6fd9b.tar.bz2 yosys-5e2562f1a2e4cfa53c80f9ca6200aecc4cc6fd9b.zip | |
opt_expr: add $alu tests
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/opt/opt_expr_alu.ys | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/tests/opt/opt_expr_alu.ys b/tests/opt/opt_expr_alu.ys new file mode 100644 index 000000000..a3361ca43 --- /dev/null +++ b/tests/opt/opt_expr_alu.ys @@ -0,0 +1,63 @@ +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b0} + 1'b1; +endmodule +EOT + +alumacc +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b1} + 1'b1; +endmodule +EOT + +alumacc +select -assert-count 1 t:$alu +select -assert-count none t:$alu t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [1:0] y); +assign y = {a,1'b1} - 1'b1; +endmodule +EOT + +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [3:0] y); +assign y = {a,3'b101} - 1'b1; +endmodule +EOT + +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D + + +design -reset +read_verilog <<EOT +module test(input a, output [3:0] y); +assign y = {a,3'b101} - 1'b1; +endmodule +EOT + +alumacc +equiv_opt opt_expr -fine +design -load postopt +select -assert-count 1 t:$pos +select -assert-count none t:$pos t:* %D |