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| author | Eddie Hung <eddie@fpgeh.com> | 2020-01-20 16:42:08 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-03 14:28:22 -0700 |
| commit | f68d723cdccdb1a604077e2a3526de2a5198123c (patch) | |
| tree | 0915d8408c793aa2785e3054f9afc1b5ea679582 /tests | |
| parent | 8e851badc49a4412a1e4a5f6881ef72647213bd9 (diff) | |
| download | yosys-f68d723cdccdb1a604077e2a3526de2a5198123c.tar.gz yosys-f68d723cdccdb1a604077e2a3526de2a5198123c.tar.bz2 yosys-f68d723cdccdb1a604077e2a3526de2a5198123c.zip | |
Refactor +/cmp2lcu.v into recursive techmap
Diffstat (limited to 'tests')
| -rw-r--r-- | tests/techmap/cmp2lcu.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/techmap/cmp2lcu.ys b/tests/techmap/cmp2lcu.ys index e7a422e2f..620996549 100644 --- a/tests/techmap/cmp2lcu.ys +++ b/tests/techmap/cmp2lcu.ys @@ -1,5 +1,5 @@ read_verilog <<EOT -module top(input [11:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les); +module top(input [12:0] a, b, output gtu, gts, ltu, lts, geu, ges, leu, les); assign gtu = a > b; assign gts = $signed(a) > $signed(b); assign ltu = a < b; |