iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	RTLIL::S{0,1} -> State::S{0,1}	Eddie Hung	2019-08-07	1	-1/+1
*	Merge remote-tracking branch 'origin/master' into eddie/cleanup	Eddie Hung	2019-08-07	2	-117/+252
\|\
\| *	Merge pull request #1260 from YosysHQ/dave/ecp5_cell_fixes	David Shah	2019-08-07	1	-101/+244
\| \|\
\| \| *	ecp5: Make cells_sim.v consistent with nextpnr	David Shah	2019-08-07	1	-101/+244
\| * \|	Merge pull request #1249 from mmicko/anlogic_fix	Clifford Wolf	2019-08-07	1	-16/+8
\| \|\ \ \| \| \|/ \| \|/\|
\| \| *	anlogic : Fix alu mapping	Miodrag Milanovic	2019-08-03	1	-16/+8
* \| \|	stoi -> atoi	Eddie Hung	2019-08-07	3	-3/+3
* \| \|	Fix spacing	Eddie Hung	2019-08-06	1	-3/+3
* \| \|	Use std::stoi instead of atoi(<str>.c_str())	Eddie Hung	2019-08-06	1	-1/+1
* \| \|	Make liberal use of IdString.in()	Eddie Hung	2019-08-06	1	-14/+8
\|/ /
* /	Add $_NMUX_, add "abc -g cmos", add proper cmos cell costs	Clifford Wolf	2019-08-06	1	-0/+19
\|/
*	Merge pull request #1239 from mmicko/mingw_fix	Clifford Wolf	2019-08-02	3	-6/+6
\|\
\| *	Fix formatting for msys2 mingw build using GetSize	Miodrag Milanovic	2019-08-01	3	-6/+6
* \|	RST -> RSTBRST for RAMB8BWER	Eddie Hung	2019-07-29	1	-3/+3
\|/
*	Merge branch 'ZirconiumX-synth_intel_m9k'	Clifford Wolf	2019-07-25	4	-5/+11
\|\
\| *	intel: Map M9K BRAM only on families that have it	Dan Ravensloft	2019-07-23	4	-5/+12
* \|	Merge pull request #1218 from ZirconiumX/synth_intel_iopads	Clifford Wolf	2019-07-25	1	-8/+8
\|\ \
\| * \|	intel: Make -noiopads the default	Dan Ravensloft	2019-07-24	1	-8/+8
* \| \|	Merge pull request #1224 from YosysHQ/xilinx_fix_ff	Eddie Hung	2019-07-25	1	-2/+2
\|\ \ \ \| \|/ / \|/\| \|
\| * \|	xilinx: Fix missing cell name underscore in cells_map.v	David Shah	2019-07-25	1	-2/+2
* \| \|	ice40: Fix test_dsp_model.sh	David Shah	2019-07-19	1	-1/+1
* \| \|	ice40/cells_sim.v: Fix sign of J and K partial products	David Shah	2019-07-19	1	-5/+7
* \| \|	ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode	David Shah	2019-07-19	1	-2/+2
* \| \|	Add tests for all combinations of A and B signedness for comb mul	Eddie Hung	2019-07-19	2	-1/+229
* \| \|	Don't copy ref if exists already	Eddie Hung	2019-07-19	1	-1/+3
\| \|/ \|/\|
* \|	Merge pull request #1208 from ZirconiumX/intel_cleanups	David Shah	2019-07-18	1	-29/+14
\|\ \
\| * \|	synth_intel: Use stringf	Dan Ravensloft	2019-07-18	1	-7/+2
\| * \|	synth_intel: s/not family/no family/	Dan Ravensloft	2019-07-18	1	-2/+2
\| * \|	intel_synth: Fix help message	Ben Widawsky	2019-07-18	1	-1/+1
\| * \|	intel_synth: Small code cleanup to remove if ladder	Ben Widawsky	2019-07-18	1	-28/+10
\| * \|	intel_synth: Make family explicit and match	Ben Widawsky	2019-07-18	1	-2/+6
\| * \|	intel_synth: Minor code cleanups	Ben Widawsky	2019-07-18	1	-2/+6
* \| \|	synth_intel: rename for consistency with #1184	Dan Ravensloft	2019-07-18	1	-4/+4
\|/ /
* \|	Merge pull request #1184 from whitequark/synth-better-labels	Clifford Wolf	2019-07-18	5	-17/+21
\|\ \
\| * \|	synth_ecp5: rename dram to lutram everywhere.	whitequark	2019-07-16	4	-13/+13
\| * \|	synth_{ice40,ecp5}: more sensible pass label naming.	whitequark	2019-07-16	2	-5/+9
* \| \|	Merge pull request #1204 from smunaut/fix_1187	David Shah	2019-07-17	2	-4/+4
\|\ \ \
\| * \| \|	ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map	Sylvain Munaut	2019-07-16	2	-4/+4
\| \| \|/ \| \|/\|
* / \|	gen_lut to return correctly sized LUT mask	Eddie Hung	2019-07-16	1	-1/+1
\|/ /
* \|	Merge pull request #1186 from YosysHQ/eddie/abc9_ice40_fix	Eddie Hung	2019-07-16	8	-29/+120
\|\ \ \| \|/ \|/\|
\| *	$__ICE40_CARRY_LUT4 -> $__ICE40_FULL_ADDER as per @whitequark	Eddie Hung	2019-07-15	7	-8/+8
\| *	ice40_opt to $__ICE40_CARRY_LUT4 into $lut not SB_LUT	Eddie Hung	2019-07-13	1	-9/+7
\| *	Use Const::from_string() not its constructor...	Eddie Hung	2019-07-12	1	-1/+1
\| *	Off by one	Eddie Hung	2019-07-12	1	-1/+1
\| *	Fix spacing	Eddie Hung	2019-07-12	1	-1/+1
\| *	Remove double push	Eddie Hung	2019-07-12	1	-1/+0
\| *	Map to and from this box if -abc9	Eddie Hung	2019-07-12	1	-2/+3
\| *	ice40_opt to handle this box and opt back to SB_LUT4	Eddie Hung	2019-07-12	1	-0/+48
\| *	Add new box to cells_sim.v	Eddie Hung	2019-07-12	1	-2/+25
\| *	_ABC macro will map and unmap to this new box	Eddie Hung	2019-07-12	2	-0/+34