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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-03 14:47:33 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-08-03 14:47:33 +0200 |
| commit | 837cb0a1b9c9a774512481d0812c28f927985e7b (patch) | |
| tree | 0f067be7a470d7974db8bf733a36c2fd0de3185b /techlibs | |
| parent | 44a9dcbbbf47f1a6f524c6328ff775f29573a935 (diff) | |
| download | yosys-837cb0a1b9c9a774512481d0812c28f927985e7b.tar.gz yosys-837cb0a1b9c9a774512481d0812c28f927985e7b.tar.bz2 yosys-837cb0a1b9c9a774512481d0812c28f927985e7b.zip | |
anlogic : Fix alu mapping
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/anlogic/arith_map.v | 24 |
1 files changed, 8 insertions, 16 deletions
diff --git a/techlibs/anlogic/arith_map.v b/techlibs/anlogic/arith_map.v index 11cd140ec..6d6a7ca37 100644 --- a/techlibs/anlogic/arith_map.v +++ b/techlibs/anlogic/arith_map.v @@ -42,10 +42,9 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); wire [Y_WIDTH-1:0] AA = A_buf; wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; wire [Y_WIDTH+1:0] COx; - wire [Y_WIDTH+1:0] C = {COx, CI}; + wire [Y_WIDTH+2:0] C = {COx, CI}; wire dummy; - (* keep *) AL_MAP_ADDER #( .ALUTYPE("ADD_CARRY")) adder_cin ( @@ -55,19 +54,6 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); genvar i; generate for (i = 0; i < Y_WIDTH; i = i + 1) begin: slice - if(i==Y_WIDTH-1) begin - (* keep *) - AL_MAP_ADDER #( - .ALUTYPE("ADD")) - adder_cout ( - .c(C[Y_WIDTH]), - .o(COx[Y_WIDTH]) - ); - assign CO = COx[Y_WIDTH]; - end - else - begin - (* keep *) AL_MAP_ADDER #( .ALUTYPE("ADD") ) adder_i ( @@ -76,9 +62,15 @@ module _80_anlogic_alu (A, B, CI, BI, X, Y, CO); .c(C[i+1]), .o({COx[i+1],Y[i]}) ); - end end: slice endgenerate /* End implementation */ + AL_MAP_ADDER #( + .ALUTYPE("ADD")) + adder_cout ( + .c(C[Y_WIDTH+1]), + .o(COx[Y_WIDTH+1]) + ); + assign CO = COx[Y_WIDTH+1]; assign X = AA ^ BB; endmodule
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