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author | David Shah <dave@ds0.me> | 2019-07-19 17:33:41 +0100 |
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committer | David Shah <dave@ds0.me> | 2019-07-19 17:33:41 +0100 |
commit | 79f14c751417685e7405855a96fc7a37f5bc7fbf (patch) | |
tree | ab0dc4cea655e22f7a6ab47e118dace542323631 /techlibs | |
parent | 3c84271543379a5a3845d5dcdb49a5e6fbafbc66 (diff) | |
download | yosys-79f14c751417685e7405855a96fc7a37f5bc7fbf.tar.gz yosys-79f14c751417685e7405855a96fc7a37f5bc7fbf.tar.bz2 yosys-79f14c751417685e7405855a96fc7a37f5bc7fbf.zip |
ice40/cells_sim.v: Fix sign of J and K partial products
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/ice40/cells_sim.v | 12 |
1 files changed, 7 insertions, 5 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 4402f8d36..2205be27d 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1366,10 +1366,10 @@ module SB_MAC16 ( assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]}; assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]}; assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]}; - assign p_Ah_Bh = Ah * Bh; - assign p_Al_Bh = Al * Bh; - assign p_Ah_Bl = Ah * Bl; - assign p_Al_Bl = Al * Bl; + assign p_Ah_Bh = Ah * Bh; // F + assign p_Al_Bh = {8'b0, Al[7:0]} * Bh; // J + assign p_Ah_Bl = Ah * {8'b0, Bl[7:0]}; // K + assign p_Al_Bl = Al * Bl; // G // Regs F and J reg [15:0] rF, rJ; @@ -1400,7 +1400,9 @@ module SB_MAC16 ( assign iG = BOT_8x8_MULT_REG ? rG : p_Al_Bl; // Adder Stage - assign iL = iG + (iK << 8) + (iJ << 8) + (iF << 16); + wire [23:0] iK_e = {A_SIGNED ? {8{iK[15]}} : 8'b0, iK}; + wire [23:0] iJ_e = {B_SIGNED ? {8{iJ[15]}} : 8'b0, iJ}; + assign iL = iG + (iK_e << 8) + (iJ_e << 8) + (iF << 16); // Reg H reg [31:0] rH; |