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author | David Shah <dave@ds0.me> | 2019-07-19 17:13:34 +0100 |
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committer | David Shah <dave@ds0.me> | 2019-07-19 17:13:34 +0100 |
commit | 3c84271543379a5a3845d5dcdb49a5e6fbafbc66 (patch) | |
tree | b138fdd5be22cca2e314409a94df92d5714021fc /techlibs | |
parent | 171cd2ff738cdb8027b9b6efb988bab8744264a9 (diff) | |
download | yosys-3c84271543379a5a3845d5dcdb49a5e6fbafbc66.tar.gz yosys-3c84271543379a5a3845d5dcdb49a5e6fbafbc66.tar.bz2 yosys-3c84271543379a5a3845d5dcdb49a5e6fbafbc66.zip |
ice40/cells_sim.v: LSB of A/B only signed in 8x8 mode
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs')
-rw-r--r-- | techlibs/ice40/cells_sim.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/ice40/cells_sim.v b/techlibs/ice40/cells_sim.v index 609facc93..4402f8d36 100644 --- a/techlibs/ice40/cells_sim.v +++ b/techlibs/ice40/cells_sim.v @@ -1363,9 +1363,9 @@ module SB_MAC16 ( wire [15:0] p_Ah_Bh, p_Al_Bh, p_Ah_Bl, p_Al_Bl; wire [15:0] Ah, Al, Bh, Bl; assign Ah = {A_SIGNED ? {8{iA[15]}} : 8'b0, iA[15: 8]}; - assign Al = {A_SIGNED ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]}; + assign Al = {A_SIGNED && MODE_8x8 ? {8{iA[ 7]}} : 8'b0, iA[ 7: 0]}; assign Bh = {B_SIGNED ? {8{iB[15]}} : 8'b0, iB[15: 8]}; - assign Bl = {B_SIGNED ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]}; + assign Bl = {B_SIGNED && MODE_8x8 ? {8{iB[ 7]}} : 8'b0, iB[ 7: 0]}; assign p_Ah_Bh = Ah * Bh; assign p_Al_Bh = Al * Bh; assign p_Ah_Bl = Ah * Bl; |