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| author | Eddie Hung <eddie@fpgeh.com> | 2019-07-25 06:44:17 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-07-25 06:44:17 -0700 |
| commit | 5248a902ef9d2e30802c3924afb19a74935adbef (patch) | |
| tree | b4ec468e7a49d3c862e969514fa0bce1ca04bb63 /techlibs | |
| parent | d6a289d3e3a09d1f11ec1588a4b4e9d6846517e8 (diff) | |
| parent | ab607e896e9f5faff939b4395b01344a36e9fc1b (diff) | |
| download | yosys-5248a902ef9d2e30802c3924afb19a74935adbef.tar.gz yosys-5248a902ef9d2e30802c3924afb19a74935adbef.tar.bz2 yosys-5248a902ef9d2e30802c3924afb19a74935adbef.zip | |
Merge pull request #1224 from YosysHQ/xilinx_fix_ff
xilinx: Fix missing cell name underscore in cells_map.v
Diffstat (limited to 'techlibs')
| -rw-r--r-- | techlibs/xilinx/cells_map.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/cells_map.v b/techlibs/xilinx/cells_map.v index 2eb9fa2c1..b8e5bafc7 100644 --- a/techlibs/xilinx/cells_map.v +++ b/techlibs/xilinx/cells_map.v @@ -24,9 +24,9 @@ module _90_dff_nn0_to_np0 (input D, C, R, output Q); \$_DFF_NP0_ _TECHMAP_REPLA (* techmap_celltype = "$_DFF_PN0_" *) module _90_dff_pn0_to_pp0 (input D, C, R, output Q); \$_DFF_PP0_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule (* techmap_celltype = "$_DFF_NN1_" *) -module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module _90_dff_nn1_to_np1 (input D, C, R, output Q); \$_DFF_NP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule (* techmap_celltype = "$_DFF_PN1_" *) -module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1 _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule +module _90_dff_pn1_to_pp1 (input D, C, R, output Q); \$_DFF_PP1_ _TECHMAP_REPLACE_ (.D(D), .Q(Q), .C(C), .R(~R)); endmodule module \$__SHREG_ (input C, input D, input E, output Q); parameter DEPTH = 0; |