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path: root/techlibs/xilinx/abc9_model.v
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* Fixing old e-mail addresses and deadnamesClaire Xenia Wolf2021-06-081-1/+1
* abc9_ops: add -prep_bypass for auto bypass boxes; refactorEddie Hung2020-05-141-171/+0
* xilinx: consider DSP48E1.ADREGEddie Hung2020-03-041-2/+3
* xilinx: cleanup DSP48E1 handling for abc9Eddie Hung2020-03-041-50/+104
* xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.vEddie Hung2020-03-041-1/+7
* abc9_ops: use TimingInfo for -prep_{lut,box} tooEddie Hung2020-02-271-7/+10
* Update xilinx for ABC9Eddie Hung2020-02-271-11/+0
* xilinx: improve specify functionalityEddie Hung2020-02-271-2/+4
* Auto-generate .box/.lut files from specify blocksEddie Hung2020-02-271-10/+80
* Merge branch 'eddie/abc9_refactor' into eddie/abc9_requiredEddie Hung2020-01-271-1/+1
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| * Fix $__ABC9_ASYNC1 to output 1'b1 not 1'b0Eddie Hung2020-01-221-1/+1
* | Add abc9_ops -check, -prep_times, -write_box for required timesEddie Hung2020-01-101-0/+5
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* Merge remote-tracking branch 'origin/master' into xaig_dffEddie Hung2020-01-061-140/+15
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| * Rework abc9's DSP48E1 modelEddie Hung2020-01-011-140/+15
* | Fix attributes on $__ABC9_ASYNC[01] whiteboxEddie Hung2019-12-311-2/+2
* | Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_tEddie Hung2019-12-191-3/+11
* | Add blackbox model for $__ABC9_FF_ so that clock partitioning worksEddie Hung2019-11-201-0/+3
* | Do not require changes to cells_sim.v; try and work out comb modelEddie Hung2019-10-051-4/+1
* | Merge remote-tracking branch 'origin/eddie/abc_to_abc9' into xaig_dffEddie Hung2019-10-041-0/+7
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* Rename abc_* names/attributes to more precisely be abc9_*Eddie Hung2019-10-041-0/+190