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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 12:04:02 -0800 |
| commit | 7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f (patch) | |
| tree | ab1520d1aa2b19eb44cb46611b425431567ca0b0 /techlibs/xilinx/abc9_model.v | |
| parent | 512596760b947a9ac9088856490970d0930dd951 (diff) | |
| download | yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.gz yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.tar.bz2 yosys-7b543fdb0cbd45dcf2d3322518cc02a01cc1e43f.zip | |
xilinx: consider DSP48E1.ADREG
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 333ac17c0..2d109ef8a 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -107,6 +107,7 @@ module $__ABC9_DSP48E1 ( output [47:0] P, output [47:0] PCOUT ); + parameter integer ADREG = 1; parameter integer AREG = 1; parameter integer BREG = 1; parameter integer CREG = 1; @@ -176,7 +177,7 @@ module $__ABC9_DSP48E1 ( // Identical comb delays to DSP48E1 in cells_sim.v generate - if (PREG == 0 && MREG == 0 && AREG == 0) + if (PREG == 0 && MREG == 0 && AREG == 0 && ADREG == 0) specify ($A *> P) = \A.P.comb (); ($A *> PCOUT) = \A.PCOUT.comb (); @@ -194,7 +195,7 @@ module $__ABC9_DSP48E1 ( ($C *> PCOUT) = \C.PCOUT.comb (); endspecify - if (PREG == 0 && MREG == 0 && DREG == 0) + if (PREG == 0 && MREG == 0 && ADREG == 0 && DREG == 0) specify ($D *> P) = \D.P.comb (); ($D *> PCOUT) = \D.PCOUT.comb (); |