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| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 22:55:18 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-05 22:55:18 -0700 |
| commit | 3879ca13983a6e3f7d4653b1d80dacd14fbe82df (patch) | |
| tree | 52fd4ecb68e7df0e0afbcb8c8333e960cc380d23 /techlibs/xilinx/abc9_model.v | |
| parent | 3c6e5d82a62650a48027d35e6d92a7a88ad43a16 (diff) | |
| download | yosys-3879ca13983a6e3f7d4653b1d80dacd14fbe82df.tar.gz yosys-3879ca13983a6e3f7d4653b1d80dacd14fbe82df.tar.bz2 yosys-3879ca13983a6e3f7d4653b1d80dacd14fbe82df.zip | |
Do not require changes to cells_sim.v; try and work out comb model
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index 74b5cf66a..c17d6744a 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -30,11 +30,8 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); : (S0 ? I1 : I0); endmodule -module \$__ABC_FF_ (input D, output Q); -endmodule - (* abc_box_id = 1000 *) -module \$__ABC_ASYNC (input A, S, output Y); +module \$__ABC9_ASYNC (input A, S, output Y); endmodule // Box to emulate comb/seq behaviour of RAMD{32,64} and SRL{16,32} |