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| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 10:32:51 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-03-04 11:31:12 -0800 |
| commit | 78d4fff69d09f46f1777213116f09826ba008991 (patch) | |
| tree | ea8424b1474f0967926feb637352f7026a69bae5 /techlibs/xilinx/abc9_model.v | |
| parent | 968956badb977984133b00c38d0a08f3e2d0b854 (diff) | |
| download | yosys-78d4fff69d09f46f1777213116f09826ba008991.tar.gz yosys-78d4fff69d09f46f1777213116f09826ba008991.tar.bz2 yosys-78d4fff69d09f46f1777213116f09826ba008991.zip | |
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index f83e97a2a..559439b85 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -113,10 +113,12 @@ module __NAME__ ( ($A *> P) = 2823; ($B *> P) = 2690; ($C *> P) = 1325; + ($PCIN *> P) = 1107; ($P *> P) = 0; ($A *> PCOUT) = 2970; ($B *> PCOUT) = 2838; ($C *> PCOUT) = 1474; + ($PCIN *> PCOUT) = 1255; ($PCOUT *> PCOUT) = 0; endspecify endmodule @@ -125,12 +127,14 @@ endmodule ($A *> P) = 3806; ($B *> P) = 2690; ($C *> P) = 1325; - ($D *> P) = 3700; + ($D *> P) = 3717; + ($PCIN *> P) = 1107; ($P *> P) = 0; ($A *> PCOUT) = 3954; ($B *> PCOUT) = 2838; ($C *> PCOUT) = 1474; ($D *> PCOUT) = 3700; + ($PCIN *> PCOUT) = 1255; ($PCOUT *> PCOUT) = 0; endspecify endmodule @@ -139,10 +143,12 @@ endmodule ($A *> P) = 1523; ($B *> P) = 1509; ($C *> P) = 1325; + ($PCIN *> P) = 1107; ($P *> P) = 0; ($A *> PCOUT) = 1671; ($B *> PCOUT) = 1658; ($C *> PCOUT) = 1474; + ($PCIN *> PCOUT) = 1255; ($PCOUT *> PCOUT) = 0; endspecify endmodule |