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| author | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 11:14:11 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-12-31 11:14:11 -0800 |
| commit | b4663a987bc1bac3aa4cccab99dc191825902205 (patch) | |
| tree | f9d589ebec3751a00090409501f502e666f23a23 /techlibs/xilinx/abc9_model.v | |
| parent | 789211d9b3a6892c72d22a09bf2299075337f9f9 (diff) | |
| download | yosys-b4663a987bc1bac3aa4cccab99dc191825902205.tar.gz yosys-b4663a987bc1bac3aa4cccab99dc191825902205.tar.bz2 yosys-b4663a987bc1bac3aa4cccab99dc191825902205.zip | |
Fix attributes on $__ABC9_ASYNC[01] whitebox
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index c793396a4..11250123d 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -34,13 +34,13 @@ module \$__ABC9_FF_ (input D, output Q); endmodule // Box to emulate async behaviour of FDC* -(* abc_box_id = 1000 *) +(* abc9_box_id = 1000, lib_whitebox *) module \$__ABC9_ASYNC0 (input A, S, output Y); assign Y = S ? 1'b0 : A; endmodule // Box to emulate async behaviour of FDP* -(* abc_box_id = 1001 *) +(* abc9_box_id = 1001, lib_whitebox *) module \$__ABC9_ASYNC1 (input A, S, output Y); assign Y = S ? 1'b0 : A; endmodule |