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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-20 14:30:56 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-20 14:30:56 -0800 |
| commit | af3055fe8354e0a082bd8415448fcbeb5ee435f6 (patch) | |
| tree | 24fb3ebdc3682a7244e710b9a4e7b393ad013916 /techlibs/xilinx/abc9_model.v | |
| parent | cd9e830b67fdffcae88dba095548995a30988fa4 (diff) | |
| download | yosys-af3055fe8354e0a082bd8415448fcbeb5ee435f6.tar.gz yosys-af3055fe8354e0a082bd8415448fcbeb5ee435f6.tar.bz2 yosys-af3055fe8354e0a082bd8415448fcbeb5ee435f6.zip | |
Add blackbox model for $__ABC9_FF_ so that clock partitioning works
Diffstat (limited to 'techlibs/xilinx/abc9_model.v')
| -rw-r--r-- | techlibs/xilinx/abc9_model.v | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/abc9_model.v b/techlibs/xilinx/abc9_model.v index c17d6744a..cc0e5ec41 100644 --- a/techlibs/xilinx/abc9_model.v +++ b/techlibs/xilinx/abc9_model.v @@ -30,6 +30,9 @@ module \$__XILINX_MUXF78 (output O, input I0, I1, I2, I3, S0, S1); : (S0 ? I1 : I0); endmodule +module \$__ABC9_FF_ (input D, output Q); +endmodule + (* abc_box_id = 1000 *) module \$__ABC9_ASYNC (input A, S, output Y); endmodule |