iCE40/yosys - [no description]

	Commit message (Expand)	Author	Age	Files	Lines
*	Auto-generate .box/.lut files from specify blocks	Eddie Hung	2020-02-27	1	-3/+0
*	xilinx: Add support for LUT RAM on LUT4-based devices.	Marcin Kościelnicki	2020-02-07	1	-1/+2
*	xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.	Marcin Kościelnicki	2020-02-07	1	-0/+3
*	xilinx: Add support for Spartan 3A DSP block RAMs.	Marcin Kościelnicki	2020-02-07	1	-0/+1
*	xilinx: Add xilinx_dffopt pass (#1557)	Marcin Kościelnicki	2019-12-18	1	-0/+1
*	synth_xilinx: Merge blackbox primitive libraries.	Marcin Kościelnicki	2019-11-06	1	-7/+1
*	xilinx: Add URAM288 mapping for xcup	David Shah	2019-10-23	1	-0/+2
*	xilinx: Add support for UltraScale[+] BRAM mapping	David Shah	2019-10-23	1	-1/+3
*	xilinx: Support multiplier mapping for all families.	Marcin Kościelnicki	2019-10-22	1	-1/+7
*	Makefile: don't assume python is called `python3`	Sean Cross	2019-10-19	1	-1/+1
*	Rename abc_* names/attributes to more precisely be abc9_*	Eddie Hung	2019-10-04	1	-6/+6
*	Revert "Add a xilinx_finalise pass"	Eddie Hung	2019-09-23	1	-1/+0
*	Add a xilinx_finalise pass	Eddie Hung	2019-09-23	1	-0/+1
*	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-18	1	-1/+4
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\| *	xilinx: Make blackbox library family-dependent.	Marcin Kościelnicki	2019-09-15	1	-1/+4
* \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-11	1	-1/+2
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\| *	synth_xilinx: Support init values on Spartan 6 flip-flops properly.	Marcin Kościelnicki	2019-09-07	1	-1/+2
* \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-09-05	1	-0/+3
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\| *	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-08-20	1	-2/+2
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\| * \|	Use abc_{map,unmap,model}.v	Eddie Hung	2019-08-20	1	-1/+3
\| * \|	Merge branch 'eddie/abc9_refactor' into xaig_dff	Eddie Hung	2019-08-16	1	-3/+12
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\| * \ \	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-07-10	1	-0/+1
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\| * \ \ \	Merge remote-tracking branch 'origin/master' into xaig_dff	Eddie Hung	2019-07-01	1	-0/+2
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\| * \| \| \| \|	Wrap FDRE with $__ABC_FDRE containing comb	Eddie Hung	2019-06-15	1	-0/+1
* \| \| \| \| \|	Merge remote-tracking branch 'origin/master' into xc7dsp	Eddie Hung	2019-08-20	1	-2/+2
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\| * \| \| \| \|	Update Makefile too	Eddie Hung	2019-07-18	1	-2/+2
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* / \| \| \|	Oops forgot these files	Eddie Hung	2019-07-15	1	-0/+1
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* \| \| /	synth_xilinx: Initial Spartan 6 block RAM inference support.	Marcin Kościelnicki	2019-07-11	1	-3/+12
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* \| \|	Merge remote-tracking branch 'origin/master' into xc7mux	Eddie Hung	2019-06-29	1	-0/+2
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\| * \|	install *_nowide.lut files	Eddie Hung	2019-06-29	1	-0/+2
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* /	Revert "Remove wide mux inference"	Eddie Hung	2019-06-14	1	-0/+1
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*	Rename +/xilinx/abc.{box,lut} -> abc_xc7.{box,lut}	Eddie Hung	2019-06-14	1	-2/+2
*	Remove wide mux inference	Eddie Hung	2019-06-12	1	-1/+0
*	Add mux_map.v for wide mux	Eddie Hung	2019-06-04	1	-0/+1
*	Cleanup, call pmux2shiftx even without -nosrl	Eddie Hung	2019-04-22	1	-3/+2
*	Add +/xilinx/cells_box.v containing models for ABC boxes	Eddie Hung	2019-04-16	1	-0/+1
*	Add cells.lut to techlibs/xilinx/	Eddie Hung	2019-04-09	1	-0/+1
*	Add techlibs/xilinx/cells.box	Eddie Hung	2019-04-09	1	-0/+1
*	Changes required for VPR place and route synth_xilinx.	Keith Rothman	2019-03-01	1	-1/+2
*	Add Xilinx RAM64X1D and RAM128X1D simulation models	Clifford Wolf	2018-03-07	1	-1/+0
*	Add techlibs/xilinx/lut2lut.v	Clifford Wolf	2017-07-10	1	-0/+1
*	Added black box modules for all the 7-series design elements (as listed in ug...	Clifford Wolf	2016-03-19	1	-0/+1
*	Switched to Python 3	Clifford Wolf	2015-08-22	1	-1/+1
*	Another bugfix for ice40 and xilinx brams_init make rules	Clifford Wolf	2015-08-16	1	-1/+1
*	Fixed Makefile rules for generated share files	Clifford Wolf	2015-08-16	1	-1/+7
*	Adjust makefiles to work with out-of-tree builds	Clifford Wolf	2015-08-12	1	-6/+2
*	Verific build fixes	Clifford Wolf	2015-05-17	1	-2/+2
*	Towards DRAM support in Xilinx flow	Clifford Wolf	2015-04-09	1	-0/+3
*	Added support for initialized xilinx brams	Clifford Wolf	2015-04-06	1	-0/+21
*	Added Xilinx bram black-box modules	Clifford Wolf	2015-04-06	1	-0/+1