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author | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:50:24 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-14 12:50:24 -0700 |
commit | b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d (patch) | |
tree | bba5b86a004118e36f753fd9b76f62ef90b70970 /techlibs/xilinx/Makefile.inc | |
parent | 691e145cda416787fe214b5533c6ac3c8047bb65 (diff) | |
download | yosys-b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d.tar.gz yosys-b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d.tar.bz2 yosys-b63b2a0bd4552a7dbe0d2c4a15d4e3a1b0e2022d.zip |
Revert "Remove wide mux inference"
This reverts commit 738fdfe8f55e18ac7f315cd68c117eae370004ca.
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
-rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 1a652eb27..59fd61cf0 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut)) |