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| author | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:20:46 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-06-12 09:20:46 -0700 |
| commit | 738fdfe8f55e18ac7f315cd68c117eae370004ca (patch) | |
| tree | 534b94c5f56dbe726b4b45f7e5dfd1280ca58312 /techlibs/xilinx/Makefile.inc | |
| parent | b2c72f74f00032d1ac5071f8bb32b87c9dc4c23e (diff) | |
| download | yosys-738fdfe8f55e18ac7f315cd68c117eae370004ca.tar.gz yosys-738fdfe8f55e18ac7f315cd68c117eae370004ca.tar.bz2 yosys-738fdfe8f55e18ac7f315cd68c117eae370004ca.zip | |
Remove wide mux inference
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 2f3945167..296edace9 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -30,7 +30,6 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut)) |