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| author | Clifford Wolf <clifford@clifford.at> | 2015-04-09 08:17:14 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2015-04-09 08:17:14 +0200 |
| commit | b00cad81d76bd83fe3210f8b84dec8c34acb7fd9 (patch) | |
| tree | 49aba5ace93677d5423d9a19a8acfc9e65f295ae /techlibs/xilinx/Makefile.inc | |
| parent | 21a1cc1b60f0c646dcc46c89440fc1a2cf606743 (diff) | |
| download | yosys-b00cad81d76bd83fe3210f8b84dec8c34acb7fd9.tar.gz yosys-b00cad81d76bd83fe3210f8b84dec8c34acb7fd9.tar.bz2 yosys-b00cad81d76bd83fe3210f8b84dec8c34acb7fd9.zip | |
Towards DRAM support in Xilinx flow
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 5253e129d..76a0cd742 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -27,5 +27,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) |