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| author | David Shah <dave@ds0.me> | 2019-10-18 13:24:19 +0100 |
|---|---|---|
| committer | David Shah <dave@ds0.me> | 2019-10-23 11:47:37 +0100 |
| commit | 6769d31ddbab341940af9b42b538fca60797fdf4 (patch) | |
| tree | a80cd15e8fdd3d4cf58ea30a7596c5d6a2a8b64b /techlibs/xilinx/Makefile.inc | |
| parent | f02623abb5d8338f034d7069844418af8912ab0f (diff) | |
| download | yosys-6769d31ddbab341940af9b42b538fca60797fdf4.tar.gz yosys-6769d31ddbab341940af9b42b538fca60797fdf4.tar.bz2 yosys-6769d31ddbab341940af9b42b538fca60797fdf4.zip | |
xilinx: Add support for UltraScale[+] BRAM mapping
Signed-off-by: David Shah <dave@ds0.me>
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 3354605ef..6fc41f591 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -32,9 +32,11 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_cells_xtra.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_xcu_brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xcu_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lutrams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) |