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| author | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 18:56:02 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-09-23 18:56:02 -0700 |
| commit | 23d90e0439ffef510632ce45a3d2aff1c129f405 (patch) | |
| tree | 8af6e6256b9e6bfe1bdf0cd9cbc3dbdcfc34bac0 /techlibs/xilinx/Makefile.inc | |
| parent | e556d48d45b0795f5fb69333b55b9f7de90ff44d (diff) | |
| download | yosys-23d90e0439ffef510632ce45a3d2aff1c129f405.tar.gz yosys-23d90e0439ffef510632ce45a3d2aff1c129f405.tar.bz2 yosys-23d90e0439ffef510632ce45a3d2aff1c129f405.zip | |
Add a xilinx_finalise pass
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index ae82311a9..10d783c3c 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -1,5 +1,6 @@ OBJS += techlibs/xilinx/synth_xilinx.o +OBJS += techlibs/xilinx/xilinx_finalise.o GENFILES += techlibs/xilinx/brams_init_36.vh GENFILES += techlibs/xilinx/brams_init_32.vh |