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| author | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:21:03 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-04-16 11:21:03 -0700 |
| commit | 3ac4977b70a373cdabaa72e5f08050f49a3d4046 (patch) | |
| tree | 282759aaef55ee6a1899ff1000094ae692a34e91 /techlibs/xilinx/Makefile.inc | |
| parent | b89bb744529fc8a5e4cd38522f86a797117f2abc (diff) | |
| download | yosys-3ac4977b70a373cdabaa72e5f08050f49a3d4046.tar.gz yosys-3ac4977b70a373cdabaa72e5f08050f49a3d4046.tar.bz2 yosys-3ac4977b70a373cdabaa72e5f08050f49a3d4046.zip | |
Add +/xilinx/cells_box.v containing models for ABC boxes
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index 432bb0770..43be55d51 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -31,6 +31,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.box)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_box.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells.lut)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) |