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| author | Clifford Wolf <clifford@clifford.at> | 2016-03-19 11:09:10 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2016-03-19 11:09:10 +0100 |
| commit | ff5c61b1207304e97714d40d37c1627510cc08a8 (patch) | |
| tree | 2757c9609c5e8fc306c70a3017949001fe2e274e /techlibs/xilinx/Makefile.inc | |
| parent | ef4207d5ade8254c9b0f63cac2ad5fee310362d4 (diff) | |
| download | yosys-ff5c61b1207304e97714d40d37c1627510cc08a8.tar.gz yosys-ff5c61b1207304e97714d40d37c1627510cc08a8.tar.bz2 yosys-ff5c61b1207304e97714d40d37c1627510cc08a8.zip | |
Added black box modules for all the 7-series design elements (as listed in ug953)
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index ccf88ec7e..5f09ffb02 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -21,6 +21,7 @@ techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) |