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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-16 16:51:22 -0700 |
| commit | 24c934f1af3859fe64ff4fb87a2a3de97695cde4 (patch) | |
| tree | 131c64cee5a0cf09adc68b32f25e06a9da668ad0 /techlibs/xilinx/Makefile.inc | |
| parent | 1c9f3fadb9f60653fc9d1d7d72ba22033e077468 (diff) | |
| parent | 5abe133323b2a6a46959f796c4730b2d70cdea26 (diff) | |
| download | yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.gz yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.tar.bz2 yosys-24c934f1af3859fe64ff4fb87a2a3de97695cde4.zip | |
Merge branch 'eddie/abc9_refactor' into xaig_dff
Diffstat (limited to 'techlibs/xilinx/Makefile.inc')
| -rw-r--r-- | techlibs/xilinx/Makefile.inc | 15 |
1 files changed, 12 insertions, 3 deletions
diff --git a/techlibs/xilinx/Makefile.inc b/techlibs/xilinx/Makefile.inc index c9a3a49fb..a9e0c5c7b 100644 --- a/techlibs/xilinx/Makefile.inc +++ b/techlibs/xilinx/Makefile.inc @@ -5,6 +5,8 @@ GENFILES += techlibs/xilinx/brams_init_36.vh GENFILES += techlibs/xilinx/brams_init_32.vh GENFILES += techlibs/xilinx/brams_init_18.vh GENFILES += techlibs/xilinx/brams_init_16.vh +GENFILES += techlibs/xilinx/brams_init_9.vh +GENFILES += techlibs/xilinx/brams_init_8.vh EXTRA_OBJS += techlibs/xilinx/brams_init.mk .SECONDARY: techlibs/xilinx/brams_init.mk @@ -18,13 +20,18 @@ techlibs/xilinx/brams_init_36.vh: techlibs/xilinx/brams_init.mk techlibs/xilinx/brams_init_32.vh: techlibs/xilinx/brams_init.mk techlibs/xilinx/brams_init_18.vh: techlibs/xilinx/brams_init.mk techlibs/xilinx/brams_init_16.vh: techlibs/xilinx/brams_init.mk +techlibs/xilinx/brams_init_9.vh: techlibs/xilinx/brams_init.mk +techlibs/xilinx/brams_init_8.vh: techlibs/xilinx/brams_init.mk $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_sim.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/cells_xtra.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams.txt)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_map.v)) -$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc6s_brams_bb.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams.txt)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_map.v)) +$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/xc7_brams_bb.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams.txt)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) @@ -41,4 +48,6 @@ $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_18.vh)) $(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_16.vh)) +$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_9.vh)) +$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_8.vh)) |